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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� UPD78F1165AGC-UEU-AX
寤犲晢锛� Renesas Electronics America
鏂囦欢闋佹暩(sh霉)锛� 503/966闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� MCU 16BIT 78K0R/KX3 100-LQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 300
绯诲垪锛� 78K0R/Kx3
鏍稿績铏曠悊鍣細 78K/0R
鑺珨灏哄锛� 16-浣�
閫熷害锛� 20MHz
閫i€氭€э細 3 绶� SIO锛孖²C锛孡IN锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 DMA锛孡VD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 83
绋嬪簭瀛樺劜鍣ㄥ閲忥細 192KB锛�192K x 8锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 10K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.8 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 16x10b; D/A 2x8b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 100-LQFP
鍖呰锛� 鎵樼洡
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CHAPTER 14 SERIAL INTERFACE IIC0
User鈥檚 Manual U17894EJ9V0UD
549
14.5 I
2C Bus Definitions and Control Methods
The following section describes the I
2C bus鈥檚 serial data communication format and the signals used by the I2C bus.
Figure 14-13 shows the transfer timing for the 鈥渟tart condition鈥�, 鈥渁ddress鈥�, 鈥渄ata鈥�, and 鈥渟top condition鈥� output via the
I
2C bus鈥檚 serial data bus.
Figure 14-13. I
2C Bus Serial Data Transfer Timing
SCL0
SDA0
Start
condition
Address R/W
ACK
Data
1-7
8
9
1-8
ACK
Data
ACK
Stop
condition
9
1-8
9
The master device generates the start condition, slave address, and stop condition.
The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device
that receives 8-bit data).
The serial clock (SCL0) is continuously output by the master device. However, in the slave device, the SCL0鈥檚 low
level period can be extended and a wait can be inserted.
14.5.1 Start conditions
A start condition is met when the SCL0 pin is at high level and the SDA0 pin changes from high level to low level.
The start conditions for the SCL0 pin and SDA0 pin are signals that the master device generates to the slave device
when starting a serial transfer. When the device is used as a slave, start conditions can be detected.
Figure 14-14. Start Conditions
SCL0
SDA0
H
A start condition is output when bit 1 (STT0) of IIC control register 0 (IICC0) is set (to 1) after a stop condition has
been detected (SPD0: Bit 0 = 1 in IIC status register 0 (IICS0)). When a start condition is detected, bit 1 (STD0) of
IICS0 is set (to 1).
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
VE-B4R-IV CONVERTER MOD DC/DC 7.5V 150W
VE-B4P-IV CONVERTER MOD DC/DC 13.8V 150W
VE-B4N-IV CONVERTER MOD DC/DC 18.5V 150W
VE-B4M-IV CONVERTER MOD DC/DC 10V 150W
VE-B4L-IV CONVERTER MOD DC/DC 28V 150W
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
UPD78F1165AGF-GAS-AX 鍔熻兘鎻忚堪:MCU 16BIT 78K0R/KX3 100-LQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - 寰帶鍒跺櫒锛� 绯诲垪:78K0R/Kx3 妯�(bi膩o)婧�(zh菙n)鍖呰:250 绯诲垪:80C 鏍稿績铏曠悊鍣�:8051 鑺珨灏哄:8-浣� 閫熷害:16MHz 閫i€氭€�:EBI/EMI锛孖²C锛孶ART/USART 澶栧湇瑷�(sh猫)鍌�:POR锛孭WM锛學DT 杓稿叆/杓稿嚭鏁�(sh霉):40 绋嬪簭瀛樺劜鍣ㄥ閲�:- 绋嬪簭瀛樺劜鍣ㄩ鍨�:ROMless EEPROM 澶у皬:- RAM 瀹归噺:256 x 8 闆诲 - 闆绘簮 (Vcc/Vdd):4.5 V ~ 5.5 V 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒:A/D 8x10b 鎸暕鍣ㄥ瀷:鍏�(n猫i)閮� 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:68-LCC锛圝 褰㈠紩绶氾級 鍖呰:甯跺嵎 (TR)
UPD78F1166AGC-UEU-AX 鍔熻兘鎻忚堪:MCU 16BIT 78K0R/KX3 100-LQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - 寰帶鍒跺櫒锛� 绯诲垪:78K0R/Kx3 妯�(bi膩o)婧�(zh菙n)鍖呰:250 绯诲垪:80C 鏍稿績铏曠悊鍣�:8051 鑺珨灏哄:8-浣� 閫熷害:16MHz 閫i€氭€�:EBI/EMI锛孖²C锛孶ART/USART 澶栧湇瑷�(sh猫)鍌�:POR锛孭WM锛學DT 杓稿叆/杓稿嚭鏁�(sh霉):40 绋嬪簭瀛樺劜鍣ㄥ閲�:- 绋嬪簭瀛樺劜鍣ㄩ鍨�:ROMless EEPROM 澶у皬:- RAM 瀹归噺:256 x 8 闆诲 - 闆绘簮 (Vcc/Vdd):4.5 V ~ 5.5 V 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒:A/D 8x10b 鎸暕鍣ㄥ瀷:鍏�(n猫i)閮� 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:68-LCC锛圝 褰㈠紩绶氾級 鍖呰:甯跺嵎 (TR)
UPD78F1166AGF-GAS-AX 鍔熻兘鎻忚堪:MCU 16BIT 78K0R/KX3 100-LQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - 寰帶鍒跺櫒锛� 绯诲垪:78K0R/Kx3 妯�(bi膩o)婧�(zh菙n)鍖呰:250 绯诲垪:80C 鏍稿績铏曠悊鍣�:8051 鑺珨灏哄:8-浣� 閫熷害:16MHz 閫i€氭€�:EBI/EMI锛孖²C锛孶ART/USART 澶栧湇瑷�(sh猫)鍌�:POR锛孭WM锛學DT 杓稿叆/杓稿嚭鏁�(sh霉):40 绋嬪簭瀛樺劜鍣ㄥ閲�:- 绋嬪簭瀛樺劜鍣ㄩ鍨�:ROMless EEPROM 澶у皬:- RAM 瀹归噺:256 x 8 闆诲 - 闆绘簮 (Vcc/Vdd):4.5 V ~ 5.5 V 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒:A/D 8x10b 鎸暕鍣ㄥ瀷:鍏�(n猫i)閮� 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:68-LCC锛圝 褰㈠紩绶氾級 鍖呰:甯跺嵎 (TR)
UPD78F1166GC-UEU-AX 鍒堕€犲晢:NEC Electronics Corporation 鍔熻兘鎻忚堪:16BIT MCU 256K FLASH 12K RAM SMD
UPD78F1166GF-GAS-AX 鍒堕€犲晢:Renesas Electronics Corporation 鍔熻兘鎻忚堪: