CHAPTER 8 WATCHDOG TIMER
User’s Manual U17854EJ9V0UD
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Remarks 1. If the overflow time is set to 2
10/fIL, the window close time and open time are as follows.
Setting of Window Open Period
25%
50%
75%
100%
Window close time
0 to 3.56 ms
0 to 2.37 ms
0 to 0.119 ms
None
Window open time
3.56 to 3.88 ms
2.37 to 3.88 ms
0.119 to 3.88 ms
0 to 3.88 ms
<When window open period is 25%>
Overflow time:
2
10/fIL (MAX.) = 210/264 kHz (MAX.) = 3.88 ms
Window close time:
0 to 2
10/fIL (MIN.)
× (1 0.25) = 0 to 210/216 kHz (MIN.) × 0.75 = 0 to 3.56 ms
Window open time:
2
10/fIL (MIN.)
× (1 0.25) to 210/fIL (MAX.) = 210/216 kHz (MIN.) × 0.75 to 210/264 kHz (MAX.)
= 3.56 to 3.88 ms
2. fIL: Internal low-speed oscillation clock frequency
8.4.4 Setting watchdog timer interval interrupt
Depending on the setting of bit 7 (WDTINT) of an option byte (000C0H), an interval interrupt (INTWDTI) can be
generated when 75% of the overflow time is reached.
Table 8-5. Setting of Watchdog Timer Interval Interrupt
WDTINT
Use of Watchdog Timer Interval Interrupt
0
Interval interrupt is used.
1
Interval interrupt is generated when 75% of overflow time is reached.
Caution
When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer overflow is
short, an overflow occurs during the oscillation stabilization time, causing a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization time when
operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the
STOP mode release by an interval interrupt.
Remark
The watchdog timer continues counting even after INTWDTI is generated (until ACH is written to the
WDTE register). If ACH is not written to the WDTE register before the overflow time, an internal reset
signal is generated.