參數(shù)資料
型號: UPD78F0034AYGB-8EU
廠商: NEC Corp.
元件分類: 8位微控制器
英文描述: 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash
中文描述: 8位微控制器與2/4/8K字節(jié)在系統(tǒng)可編程閃存
文件頁數(shù): 44/66頁
文件大?。?/td> 565K
代理商: UPD78F0034AYGB-8EU
μ
PD78F0034A, 78F0034AY
44
Data Sheet U14040EJ4V0DS
A/D Converter Characteristics (T
A
=
40 to +85
°
C, V
DD
= AV
DD
= AV
REF
= 1.8 to 5.5 V, AV
SS
= V
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Resolution
10
10
10
bit
Overall error
Note
4.0 V
AV
REF
5.5 V
±
0.2
±
0.4
%FSR
2.7 V
AV
REF
< 4.0 V
±
0.3
±
0.6
%FSR
1.8 V
AV
REF
< 2.7 V
±
0.6
±
1.2
%FSR
Conversion time
t
CONV
4.0 V
AV
REF
5.5 V
14
96
μ
s
2.7 V
AV
REF
< 4.0 V
19
96
μ
s
1.8 V
AV
REF
< 2.7 V
28
96
μ
s
Zero-scale error
Notes 1, 2
4.0 V
AV
REF
5.5 V
±
0.4
%FSR
2.7 V
AV
REF
< 4.0 V
±
0.6
%FSR
1.8 V
AV
REF
< 2.7 V
±
1.2
%FSR
Full-scale error
Notes 1, 2
4.0 V
AV
REF
5.5 V
±
0.4
%FSR
2.7 V
AV
REF
< 4.0 V
±
0.6
%FSR
1.8 V
AV
REF
< 2.7 V
±
1.2
%FSR
Integral linearity error
Note 1
4.0 V
AV
REF
5.5 V
±
2.5
LSB
2.7 V
AV
REF
< 4.0 V
±
4.5
LSB
1.8 V
AV
REF
< 2.7 V
±
8.5
LSB
Differential linearity error
4.0 V
AV
REF
5.5 V
±
1.5
LSB
2.7 V
AV
REF
4.0 V
±
2.0
LSB
1.8 V
AV
REF
< 2.7 V
±
3.5
LSB
Analog input voltage
V
IAN
0
AV
REF
V
Reference voltage
AV
REF
1.8
AV
DD
V
Resistance between AV
REF
and AV
SS
R
REF
During A/D conversion operation
20
40
k
Notes 1.
Excluding quantization error (
±
1/2 LSB).
2.
Indicated as a ratio to the full-scale value (%FSR).
Remark
When the
μ
PD78F0034A or 78F0034AY is used as an 8-bit resolution A/D converter, the specifications
are the same as for the
μ
PD780024A or 78F0024AY Subseries A/D converter.
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T
A
=
40 to +85
°
C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Data retention supply voltage
V
DDDR
1.6
5.5
V
Data retention supply current
I
DDDR
Subsystem clock stop (XT1 = V
DD
)
and feed-back resistor disconnected
0.1
30
μ
A
Release signal set time
t
SREL
0
μ
s
Oscillation stabilization wait time
t
WAIT
Release by RESET
2
17
/f
X
s
Release by interrupt request
Note
s
Note
Selection of 2
12
/f
X
and 2
14
/f
X
to 2
17
/f
X
is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
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