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參數(shù)資料
| 型號： | UPD784218YGF |
| 廠商： | NEC Corp. |
| 英文描述： | DB15 RJ11 ADAPTER KIT FEMA |
| 中文描述： | 16-/8-bit的單晶片微控制器 |
| 文件頁數(shù)： | 64/92頁 |
| 文件大小： | 617K |
| 代理商： | UPD784218YGF |
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μ
PD784218, 784218Y
Data Sheet U12304EJ2V0DS00
64
Main System Clock Oscillator Characteristics (T
A
= –40 to +85
°
C)
Resonator Recommended Circuit
Parameter
Test Conditions
MIN.
TYP.
MAX.
Unit
Ceramic
resonator
or crystal
resonator
Oscillation
frequency (f
X
)
4.5 V
≤
V
DD
≤
5.5 V
2
12.5
MHz
2.7 V
≤
V
DD
< 4.5 V
2
6.25
2.2 V
≤
V
DD
< 2.7 V
2
3
External
X1 input frequency
4.5 V
≤
V
DD
≤
5.5 V
2
25
MHz
clock
(f
X
)
2.7 V
≤
V
DD
< 4.5 V
2
12.5
2.2 V
≤
V
DD
< 2.7 V
2
6.25
X1 input high-/low-
level width
(t
WXH
, t
WXL
)
15
250
ns
X1 input rise/fall
time (t
XR
, t
XF
)
4.5 V
≤
V
DD
≤
5.5 V
0
5
ns
2.7 V
≤
V
DD
< 4.5 V
0
10
2.2 V
≤
DD
< 2.7 V
0
20
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as V
SS
.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the device is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
Remark
For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
X2
X1 V
SS
X2
X1
PD74HCU04
μ
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