參數(shù)資料
型號(hào)： UPD784038Y
廠商： NEC Corp.
英文描述： 16-/8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 16-/8-bit的單晶片微控制器
文件頁數(shù)： 73/94頁
文件大?。?/td> 503K
代理商： UPD784038Y
73
μ
PD784035Y, 784036Y, 784037Y, 784038Y
CLOCK OUTPUT OPERATION
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
CLKOUT cycle time
t
CYCL
nT
ns
CLKOUT low-level width
t
CLL
V
DD
= +5.0 V
±
10%
0.5t
CYCL
–10
ns
0.5t
CYCL
–20
ns
CLKOUT high-level width
t
CLH
V
DD
= +5.0 V
±
10%
0.5t
CYCL
–10
ns
0.5t
CYCL
–20
ns
CLKOUT rising time
t
CLR
V
DD
= +5.0 V
±
10%
10
ns
20
ns
CLKOUT falling time
t
CLF
V
DD
= +5.0 V
±
10%
10
ns
20
ns
Remark
n: Divided frequency ratio set by software in the CPU (n = 1, 2, 4, 8, 16)
T: t
CYK
(system clock cycle time)
OTHER OPERATIONS
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
NMI low-level width
t
WNIL
10
μ
s
μ
s
NMI high-level width
t
WNIH
10
INTP0 low-level width
t
WIT0L
3t
CYSMP
+10
ns
INTP0 high-level width
t
WIT0H
3t
CYSMP
+10
ns
INTP1 to INTP3, CI
low-level width
t
WIT1L
3t
CYCPU
+10
ns
INTP1 to INTP3, CI
high-level width
t
WIT1H
3t
CYCPU
+10
ns
INTP4, INTP5 low-level
width
t
WIT2L
10
μ
s
INTP4, INTP5 high-level t
WIT2H
width
10
μ
s
RESET low-level width
t
WRSL
10
μ
s
μ
s
RESET high-level width
t
WRSH
10
Remark
t
CYSMP
: Sampling clock set by software
t
CYCPU
: CPU operation clock set by software in the CPU
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