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參數(shù)資料
| 型號： | UPD780824 |
| 廠商： | NEC Corp. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash |
| 中文描述： | 8位微控制器與2/4/8K字節(jié)在系統(tǒng)可編程閃存 |
| 文件頁數(shù)： | 34/52頁 |
| 文件大小： | 345K |
| 代理商： | UPD780824 |
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34
μ
PD780232
Data Sheet U13415EJ2V0DS
Capacitance (T
A
= 25
°
C, V
DD
= V
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
f = 1 MHz
Unmeasured pins returned to 0 V
P00 to P02, P20 to P27
15
pF
P50 to P57, P60 to P64
35
pF
Output capacitance
C
OUT
f = 1 MHz
Unmeasured pins returned to 0 V
P00 to P02, P20 to P27
15
pF
P30 to P37, P40 to P47,
P50 to P57, P60 to P64,
FIP0 to FIP23
35
pF
I/O
capacitance
C
IO
f = 1 MHz
Unmeasured pins returned to 0 V
P00 to P02, P20 to P27
15
pF
P50 to P57, P60 to P64
35
pF
DC Characteristics (T
A
= –40 to +85
°
C, V
DD
= 4.5 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input voltage, high
V
IH1
P00 to P02, P20 to P27, RESET
0.7V
DD
V
DD
V
V
IH2
P50 to P57, P60 to P64
0.7V
DD
V
DD
V
V
IH3
X1, X2
V
DD
– 0.5
V
DD
V
Input voltage, low
V
IL1
P00 to P02, P20 to P27, RESET
0
0.2V
DD
V
V
IL2
X1, X2
0
0.4
V
Output voltage, high
V
OH
I
OH
= –1 mA
V
DD
– 1.0
V
DD
V
I
OH
= –100
μ
A
V
DD
– 0.5
V
DD
V
Output voltage, low
V
OL
P00 to P02, P20 to P27
I
OL
= 400
μ
A
0.5
V
Input leakage
current, high
I
LIH1
P00 to P02, P20 to P27, P50 to P57, P60 to P64, RESET
V
IN
= V
DD
3
μ
A
I
LIH2
X1, X2
20
μ
A
Input leakage
current, low
I
LIL1
P00 to P02, P20 to P27, RESET
V
IN
= 0 V
–3
μ
A
I
LIL2
X1, X2
–20
μ
A
I
LIH3
P50 to P57, P60 to P64
V
IN
= V
LOAD
= V
DD
– 40 V
–10
μ
A
Output leakage
current, high
I
LOH
P00 to P02, P20 to P27, P30 to P37,
P40 to P47, P50 to P57, P60 to P64
V
OUT
= V
DD
3
μ
A
Output leakage
current, low
I
LOL1
P00 to P02, P20 to P27
V
OUT
= 0 V
–3
μ
A
I
LOL2
P30 to P37, P40 to P47, P50 to P57, P60 to P64
V
OUT
= V
LOAD
= V
DD
– 40 V
–10
μ
A
VFD output current
I
OD
FIP0 to FIP19
V
OD
= V
DD
– 2 V
–15
mA
FIP20 to FIP52
–5
mA
Software pull-up
resistance
R
1
P00 to P02, P20 to P27
V
IN
= 0 V
10
30
100
k
On-chip mask option
pull-down resistance
(V
SS0
connection)
R
2
P50 to P57, P60 to P64
15
35
90
k
On-chip mask option
pull-down resistance
(V
LOAD
connection)
R
3
FIP0 to FIP52
V
OD
– V
LOAD
= 40 V
30
60
135
k
Power supply
current
Note
I
DD1
5 MHz crystal oscillation operation mode
PCC = 00H
7
14
mA
I
DD2
5 MHz crystal oscillation HALT mode
1.5
4.5
mA
I
DD3
STOP mode
1
30
μ
A
Note
Refers to the current flowing to the V
DD
pin. The current flowing to the on-chip pull-up and pull-down resistors is not included.
Remarks 1.
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
2.
PCC: Processor clock control register
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