參數(shù)資料
型號(hào)： UPD78002
廠商： NEC Corp.
元件分類： DC/DC變換器
英文描述： 1 watt dc-dc converters
中文描述： 1瓦的DC - DC轉(zhuǎn)換器
文件頁(yè)數(shù)： 37/62頁(yè)
文件大?。?/td> 576K
代理商： UPD78002
μ
PD78001B(A), 78002B(A)
37
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
ASTB high-level width
t
ASTH
0.5t
CY
ns
Address setup time
t
ADS
0.5t
CY
–30
ns
Address hold time
t
ADH
Load resistor
≥
5 k
10
ns
Data input time from address
t
ADD1
(2+2n)t
CY
–50
ns
t
ADD2
5
(3+2n)t
CY
–100
ns
Data input time from RD
↓
t
RDD1
(1+2n)t
CY
–25
ns
t
RDD2
(2.5+2n)t
CY
–100
ns
Read data hold time
t
RDH
0
ns
RD low-level width
t
RDL1
(1.5+2n)t
CY
–20
ns
t
RDL2
(2.5+2n)t
CY
–20
ns
WAIT
↓
input time from RD
↓
t
RDWT1
0.5t
CY
ns
t
RDWT2
1.5t
CY
ns
WAIT
↓
input time from WR
↓
t
WRWT
0.5t
CY
ns
WAIT low-level width
t
WTL
(0.5+2n)t
CY
+10
(2+2n)t
CY
ns
Write data setup time
t
WDS
100
ns
Write data hold time
t
WDH
5
ns
WR low-level width
t
WRL1
(2.5+2n)t
CY
–20
ns
RD
↓
delay time from ASTB
↓
t
ASTRD
0.5t
CY
–30
ns
WR
↓
delay time from ASTB
↓
t
ASTWR
1.5t
CY
–30
ns
ASTB
↑
delay time from
t
RDAST
t
CY
-10
t
CY
+40
ns
RD
↑
in external fetch
Address hold time from
t
RDADH
t
CY
t
CY
+50
ns
RD
↑
in external fetch
Write data output time from RD
↑
t
RDWD
10
ns
WR
↓
delay time from write data
t
WDWR
V
DD
= 4.5 to 6.0 V
0.5t
CY
–120
0.5t
CY
ns
0.5t
CY
–170
0.5t
CY
ns
Address hold time from WR
↑
t
WRADH
V
DD
=4.5 to 6.0 V
t
CY
t
CY
+60
ns
t
CY
t
CY
+100
ns
RD
↑
delay time from WAIT
↑
t
WTRD
0.5t
CY
2.5t
CY
+80
ns
WR
↑
delay time from WAIT
↑
t
WTWR
0.5t
CY
2.5t
CY
+80
ns
(2) Read/Write Operation
(T
A
= –40 to +85
°
C, V
DD
= 2.7 to 6.0 V)
Remarks
1.
t
CY
= T
CY
/4
n indicates number of waits.
C
L
= 100 pF (C
L
indicates load capacitance of P40/AD0 to P47/AD7, P50/A8 to P57/A15, P64/RD, P65/WR,
P66/WAIT,P67/ASTB pins).
2.
3.
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