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參數(shù)資料
| 型號： | UPD78001BCWA |
| 廠商： | NEC Corp. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | 1 watt dc-dc converters |
| 中文描述： | 1瓦的DC - DC轉(zhuǎn)換器 |
| 文件頁數(shù)： | 31/62頁 |
| 文件大?。?/td> | 576K |
| 代理商： | UPD78001BCWA |
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μ
PD78001B(A), 78002B(A)
31
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
f=1 MHz Unmeasured pins returned to 0 V
15
pF
I/O capacitance
P01 to P03, P10 to P17,
P20 to P27, P30 to P37,
15
pF
C
IO
P40 toP47, P50 to P57,
P64 to P67
P60 to P63
20
pF
Capacitance
(T
A
= 25
°
C, V
DD
= V
SS
= 0 V)
f=1 MHz Unmeasured
pins returned to 0 V
Remark
The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
Main System Clock Oscillation Circuit Characteristics
(T
A
= –40 to +85
°
C, V
DD
= 2.7 to 6.0 V)
Parameter
Oscillator
frequency (f
X
)
*1
Oscillation
stabilization time
*2
Oscillator
frequency (f
X
)
*1
Oscillation
stabilization time
*2
X1 input
frequency (f
X
)
*1
X1 input
high/low level width
(t
XH
, t
XL
)
Unit
MHz
ms
MHz
ms
MHz
ns
Resonator
Ceramic
resonator
Crystal
resonator
External
clock
Recommended
Circuit
Test Conditions
V
DD
= Oscillator
voltage range
After V
DD
reaches oscil-
lator voltage range MIN.
V
DD
= 4.5 to 6.0 V
MIN.
1
1
1.0
42.5
TYP.
8.38
MAX.
10
4
10
10
30
10.0
500
μ
PD74HCU04
*
1.
Indicates only oscillation circuit characteristics. Refer to “AC Characteristics” for instruction execution time.
Time required to stabilize oscillation after reset or STOP mode release.
2.
Cautions
1.
When using the main system clock oscillator, wiring the area enclosed with the broken line should be carried
out as follows to avoid an adverse effect from wiring capacitance.
Wiring should be as short as possible.
Wiring should not cross other signal lines.
Wiring should not be placed close to a varying high current.
The potential of the oscillator capacitor ground should be the same as VSS.
Do not ground wiring to a ground pattern in which a high current flows.
Do not fetch a signal from the oscillator.
2.
When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem
clock should be switched again to the main system clock after the oscillation stabilization time is secured by
the program.
X1
X2
C2
C1
R1
V
SS
X1
X2
C2
C1
V
SS
X1
X2
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