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參數(shù)資料
| 型號： | UPD765B |
| 廠商： | NEC Corp. |
| 英文描述： | Single/Double Density Floppy-Disk Controller |
| 中文描述： | 單/雙密度軟盤控制器 |
| 文件頁數(shù)： | 9/17頁 |
| 文件大?。?/td> | 344K |
| 代理商： | UPD765B |
NEC
uPD765A /uPD765B
liming Waveforms (Cont)
Write Clock
Index
I
INDEX
Internal
The
may be accessed by the main system processor: a sta-
tus register and a data register. The
8-bit
main status
register contains the status information of the FDC, and
may be accessed at any time. The
8-bit
data register
(which actually consists of four registers,
STO-ST3,
stack with only one register presented to the data bus at
a time), stores data, commands, parameters, and FDD
status information. Data bytes are read out of, or written
into, the data register in order to program or obtain the
results after a particular command (table 3). Only the
status register may be read and used to facilitate the
transfer of data between the processor and
uPD765A/
uPD765B.
The relationship between the status/data registers and
the signals RD, WR, and
A0
is shown in table 1.
Registers
uPD765A/uPD765B
contains two registers which
in a
Table 1.
Status/Data
Register
Addressing
A0
0
0
RD
WR
Funct i on
1
Read
main
status
register
Illegal
Illegal
Illegal
Read fromdata register
Write
into
data register
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
The bits in the main status register are defined in
table 2.
Table 2. Main Status Register
No.
Name
Function
DB0
D0B
(FDD 0 Busy)
FDD number 0 is in the seek mode. II any
of the
DnB
bits
IS
set FDC will not accept
read or write command.
DB1
D1B
(FDD 1 Busy)
FDD number1 is
in
the seek
mode.
If any of
the
DnB
bits
IS
set FDC
will
not accept read
or
write
command.
DB2
D2B
(FDD
2 Busy)
FDD number 2 is
in
the seek mode If any
of the
DnB bits
IS
set FDC
will
not acceot
read or write command
FDD number 3 is
in
the seek mode. If any
of the
DnB
bits
set FDC
will
not
accept
read or write command
DB3
D3B
(FDD
3 Busy)
DB4
CB
(FDC
Busy)
E X M
(Execution
A Read or Write command is
in orocess.
FDC
will
not accept any other command.
This bit is set only
during
execution
in non-DMA mode When
DB5
goes low,
execution
phase has ended and result
phase has started. It operates only
during
non-DMA mode of
operation
Indicates
direction
of data transfer be-
DB5
ohase
Mode)
D6
DIO
(Data Input/Output) tween FDC and data regrster If
DIO= 1
then transfer is fromdata
register
to the
processor. If
DIO = 0,
then transfer is from
the processor to data register.
RQM
Indicates
data register
IS
ready to send or
(Request for Master)
receive data to or fromthe processor Both
bits
DIO
and
RQM
should be used to per-
formthe hand-shaking functions of
“ready” and “directron”
to the
processor
DB7
The DIO and RQM bits in the status register indicate
when data is ready and in which direction data will be
transferred on the data bus. See figure 1.
Figure 1.
DIO
and RQM
Data In/Out
(DIO)
Out FDC and Into Processor
Out
Processor and Into FDC
II
C
5-l 1
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