參數(shù)資料
型號(hào)： UPD754264GS
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 4位單晶片微控制器
文件頁(yè)數(shù)： 33/68頁(yè)
文件大?。?/td> 318K
代理商： UPD754264GS
33
μ
PD754264
10.2 Watchdog Flag (WDF), Key Return Flag (KRF)
The WDF is cleared by a watchdog timer overflow signal, and the KRF is set by a reset signal generated by the
KRn pins. As a result, by checking the contents of WDF and KRF, it is possible to know what kind of reset signal
is generated.
As the WDF and KRF are cleared only by external signal or instruction execution, if once these flags are set, they
are not cleared until an external signal is generated or a clear instruction is executed. Check and clear the contents
of WDF and KRF after reset start operation by executing SKTCLR instruction and so on.
Table 10-2 lists the contents of WDF and KRF corresponding to each signal. Figure 10-3 shows the WDF operation
in generating each signal, and Figure 10-4 shows the KRF operation in generating each signal.
Table 10-2. WDF and KRF Contents Correspond to Each Signal
External RESET
signal generation
Reset signal
generation by watch-
generation by the
dog timer overflow
Reset signal
WDF clear
instruction
execution
KRF clear
instruction
execution
Hardware
KRn input
Watchdog flag (WDF)
0
1
Hold
0
Hold
Key return flag (KRF)
0
Hold
1
Hold
0
Figure 10-3. WDF Operation in Generating Each Signal
External RESET
WDF
Operation mode
Reset signal generation by
watchdog timer overflow
External RESET
signal generation
WDF clear
instruction
execution
Operation mode
HALT
mode
Operation
mode
HALT
mode
Operation
mode
HALT
mode
Operation mode
Internal reset operation
Internal reset operation
Internal reset operation
Reset signal generation by
watchdog timer overflow
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