參數(shù)資料
型號(hào)： UPD753204GT
廠(chǎng)商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 4位單晶片微控制器
文件頁(yè)數(shù)： 67/80頁(yè)
文件大?。?/td> 577K
代理商： UPD753204GT
67
μ
PD753204, 753206, 753208
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS
(T
A
= –40 to +85C)
Parameter
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
Release signal set time
t
SREL
0
μ
s
Oscillation stabilization
wait time
Note 1
t
WAIT
Release by RESET
Note 2
ms
Release by interrupt
Note 3
ms
Notes 1.
The oscillation stabillization wait time is the time during which the CPU operation is stopped to prevent
unstable operation at the oscillation start.
2.
Either 2
17
/f
X
or 2
15
/f
X
can be selected by the mask option.
3.
Depends on the basic interval timer mode register (BTM) settings (See the table below).
BTM3
BTM2
BTM1
BTM0
Wait time
When fx = 4.19-MHz operation When fx = 6.0-MHz operation
2
20
/f
X
(approx. 250 ms)
2
17
/f
X
(approx. 31.3 ms)
2
15
/f
X
(approx. 7.81 ms)
2
13
/f
X
(approx. 1.95 ms)
—
—
—
—
0
0
1
1
0
1
0
1
0
1
1
1
2
20
/f
X
(approx. 175 ms)
2
17
/f
X
(approx. 21.8 ms)
2
15
/f
X
(approx. 5.46 ms)
2
13
/f
X
(approx. 1.37 ms)
Data Retention Timing (STOP Mode Release by RESET)
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
V
DD
RESET
STOP Instruction Execution
STOP Mode
Data Retention Mode
Internal Reset Operation
Halt mode
Operating Mode
t
SREL
t
WAIT
t
SREL
t
WAIT
V
DD
STOP Instruction Execution
STOP Mode
Data Retention Mode
Halt mode
Operating Mode
Standby Release Signal
(Interrupt Request)
相關(guān)PDF資料
PDF描述
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