
44
μ
PD75304B,75306B,75308B
Operation
Skip Condition
Operand
Address-
ing Area
A, PORTn
XA, PORTn
PORTn, A
PORTn, XA
MBn
taddr
2
2
2
2
2
2
1
2
1
-----------------------------------------------------------------
TCALL Instruction
(SP – 4) (SP – 1) (SP – 2)
←
PC
11–0
(SP – 3)
←
MBE, 0, 0, 0
PC
11–0
←
(taddr)
3–0
←
(taddr + 1)
SP
←
SP – 4
-----------------------------------------------------------------
Other than TBR and TCALL Instruction
Execution of an instruction addressed at
(taddr) and (taddr + 1)
-----------------------------
Conforms to
referenced
instruction.
Conforms to
referenced
instruction.
-----------------------------------------------------------------
TCALL Instruction
(SP – 4) (SP – 1) (SP – 2)
←
PC
11–0
(SP – 3)
←
MBE, 0, 0, PC
12
PC
12–0
←
(taddr)
4–0
←
(taddr + 1)
SP
←
SP – 4
-----------------------------------------------------------------
Other than TBR and TCALL Instruction
Execution of an instruction addressed at
(taddr) and (taddr + 1)
-----------------------------
-----------------------------
*
At IN/OUT instruction execution, MBE = 0 or MBE = 1, MBS = 15 must be set in advance.
*10
Note
1.
Instruction Group
2.
CPU control
Remarks
The TBR and TCALL instructions are assembler pseudo-instructions for GETI instruction table
definition.
Note
1
Mne-
monic
IN
*
OUT
*
HALT
STOP
NOP
SEL
GETI
S
I
N
BytesCycles
2
2
2
2
2
2
1
2
3
A
←
PORT
n
(n = 0–7)
XA
←
PORT
n+1
, PORT
n
(n = 4, 6)
PORT
n
←
A
(n = 2–7)
PORT
n+1
, PORT
n
←
XA
(n =4, 6)
Set HALT Mode (PCC.2
←
1)
Set STOP Mode (PCC.3
←
1)
No Operation
MBS
←
n (n = 0, 1, 15)
G
μ
PD75304B
TBR Instruction
PC
(taddr)
+ (taddr + 1)
G
μ
PD75306, 75308BB
TBR Instruction
PC
(taddr)
+ (taddr + 1)
-----------------------------