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參數(shù)資料
| 型號(hào)： | UPD75236 |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機(jī) |
| 文件頁(yè)數(shù)： | 75/190頁(yè) |
| 文件大小： | 1220K |
| 代理商： | UPD75236 |
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75
μ
PD75236
(4)
Configuration and operation for use in the PWM pulse generate mode
The timer/pulse generator for use in the PWM pulse generate mode is shown in Fig. 4-34.
The PWM pulse generate mode is selected by setting TPGM0 to “0”. Pulse output is enabled by setting
TPGM5 and TPGM7 to “1”. In the PWM mode, PWM pulse can be output from the PPO pin and the
IRQTPG can be set at the fixed interval (2
15
/f
X
= 7.81 ms : at 4.19 MHz operation).
The PWM pulse generated by the
μ
PD75236 is an active-low, 14-bit accuracy pulse. This pulse is
converted to an analog voltage by integrating it using an external low-pass filter and can be applied for
electronic tuning and DC motor control. (Refer to
Fig. 4-35 Example of D/A Conversion Configuration with
μ
PD75236.
)
The PWM pulse is generated by combining the fundamental period determined by 2
10
/f
X
(244
μ
s: at 4.19
MHz operation) and the sub period of 2
15
/f
X
(7.81 ms: at 4.19 MHz operation) and the time constant of the
external low-pass filter can be shortened.
The low-level width of the PWM pulse is determined by the 14-bit modulo latch value. The modulo
latch value is determined as a result of transfer of MODH 8 bits to the most significant 8 bits of the
modulo latch and MODL most significant 6 bits to the least significant 6 bits of the modulo latch.
The digital-to analog converted output voltage is given as
In the
μ
PD75236, all 14 bits can be transferred simultaneously to the modulo latch after correct data has
been written to MODH and MODL by the 8-bit manipulation instruction. This aims at preventing the PWM
from being generated with an unstable value in the process of modulo latch rewrite. This transfer is called
“reload” and is controlled by TPGM3.
Note
1. Setting “0” to modulo register H (MODH) disables the PWM pulse generator to operate normally.
Be sure to set to MODH a value in the range from 1 to 255.
2. When the least significant 2 bits of modulo register L (MODL) are read, an undefined value is read.
3. The fundamental period of the PWM pulse is 2
10
/f
X
(244
μ
s: at 4.19 MHz operation). If the module
latch is changed with a shorter period, the PWM pulse remains unchanged.
(5)
Static output to the PPO pin
If pulse output is not necessary, the PPO pin can be used for normal static output. In this case, set
output data to TPGM4 with TPGM5 and TPGM7 set to “0” and “1”, respectively.
V
AN
= V
ref
×
where V
ref
: External switching circuit reference voltage
Modulo latch value
2
14
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