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參數(shù)資料
| 型號(hào)： | UPD75208CW |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機(jī) |
| 文件頁(yè)數(shù)： | 23/62頁(yè) |
| 文件大?。?/td> | 497K |
| 代理商： | UPD75208CW |
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23
μ
PD75208
5.9
POWER-ON FLAG (MASK OPTION)
The power-on flag (PONF) is automatically set (1) when the power-on reset circuit is activated and the power-
on reset signal is generated. (See
Fig. 8-1 Reset Signal Generator
)
The PONF is mapped at bit 0 of address FD1H in the data memory space and can be tested by the memory bit
manipulation instructions (SKT, SKF, SKTCLR) or cleared (CLR1).
Note
The PONF cannot be set by SET1 instruction.
6.
INTERRUPT FUNCTIONS
The
μ
PD75208 has eight types of interrupt sources and can generate multiple interrupts with priority order.
It is also equipped with two types of test sources. INT2 is an edge detected testable input.
The
μ
PD75208 interrupt control circuit has the following functions:
Hardware-controller vectored interrupt function which can control interrupt acknowledge with the interrupt
enable flag (IE
×××
) and the interrupt master enable flag (IME).
Function of setting any interrupt start address.
Multiple interrupt function which can specify priority order with the interrupt priority select register (IPS).
Interrupt request flag (IRQ
×××
) test function. (Interrupt generation can be checked by software.)
Standby mode release function. (Interrupt to be released by interrupt enable flag can be selected.)
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