參數(shù)資料
型號: UPD75206GF
廠商: NEC Corp.
英文描述: 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述: 4位單片機(jī)
文件頁數(shù): 15/62頁
文件大?。?/td> 489K
代理商: UPD75206GF
15
μ
PD75206
5.2
CLOCK GENERATOR CIRCUIT
The operation of the clock generator circuit is determined by the processor clock control register (PPC) and
system clock control register (SCC).
This circuit can generate two types of clocks: main system clock and subsystem clock.
In addition, it can also change the instruction execution time.
0.95
μ
s, 1.91
μ
s, 15.3
μ
s (main system clock: 4.19 MHz)
122
μ
s (subsystem clock: 32.768 kHz)
Fig. 5-1 Clock Generator Block Diagram
XT1
XT2
X1
X2
f
XT
f
X
SCC
PCC
HALT
*
STOP
*
HALT F/F
STOP
F/F
4
Q
S
R
S
R
1/4
1/8~1/4096
SCC3
SCC0
PCC0
PCC1
PCC2
PCC3
Q
S
f
XX
1/2 1/6
Frequency Divider
S
Watch Timer
Timer/Pulse
Generator
Subsystem
Clock
Generator
Main System
Clock
Generator
Oscillation
Stop
Frequency
Divider
FIP Controller
Basic Interval Timer (BT)
Timer/Event Counter
Serial Interface
Watch Timer
INT0 Noise Eliminator
CPU
INT0 Noise Eliminator
INT1 Noise Eliminator
Φ
Wait Release Signal from BT
RES Signal (Internal Reset)
Standby Release Signal from
Interrupt Control Circuit
PCC2 and
PCC3
Clear
I
*
Instruction execution
Remarks
1.
2.
3.
4.
5.
6.
7.
f
X
= Main system clock frequency
f
XT
= Subsystem clock frequency
f
XX
= System clock frequency
Φ
= CPU clock
PCC: Processor clock control register
SCC: System clock control register
1 clock cycle (t
CY
) of
Φ
is 1 machine cycle of an instruction. For t
CY
, see ”AC Characteristics“ in
12.
ELECTRICAL SPECIFICATIONS.
#
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