32
μ
PD75206
mem.bit
2
2
(mem.bit)
←
1
*3
fmem.bit
2
2
(fmem.bit)
←
1
*4
pmem.@L
2
2
(pmem
7–2
+L
3–2
.bit(L
1–0
))
←
1
*5
@H + mem.bit
2
2
(H+mem
3–0
.bit)
←
1
*1
mem.bit
2
2
(mem.bit)
←
0
*3
fmem.bit
2
2
(fmem.bit)
←
0
*4
pmem.@L
2
2
(pmem
7–2
+L
3–2
.bit(L
1–0
))
←
0
*5
@H+mem.bit
2
2
(H+mem
3–0
.bit)
←
0
*1
mem.bit
2
2 + S
Skip if (mem.bit) = 1
*3
(mem.bit) = 1
fmem.bit
2
2 + S
Skip if (fmem.bit) = 1
*4
(fmem.bit) = 1
pmem.@L
2
2 + S
Skip if (pmem
7–2
+L
3–2
.bit(L
1–0
)) = 1
*5
(pmem.@L) = 1
@H+mem.bit
2
2 + S
Skip if (H+mem
3–0
.bit) = 1
*1
(@H+mem.bit) = 1
mem.bit
2
2 + S
Skip if (mem.bit) = 0
*3
(mem.bit) = 0
fmem.bit
2
2 + S
Skip if (fmem.bit) = 0
*4
(fmem.bit) = 0
pmem.@L
2
2 + S
Skip if (pmem
7–2
+L
3–2
.bit(L
1–0
)) = 0
*5
(pmem.@L) = 0
@H+mem.bit
2
2 + S
Skip if (H+mem
3–0
.bit) = 0
*1
(@H+mem.bit)= 0
fmem.bit
2
2 + S
Skip if (fmem.bit) = 1 and clear
*4
(fmem.bit) = 1
pmem.@L
2
2 + S
Skip if (pmem
7–2
+L
3–2
.bit(L
1–0
))=1 and clear
*5
(pmem.@L) = 1
@H+mem.bit
2
2 + S
Skip if (H+mem
3–0
.bit)=1 and clear
*1
(@H+mem.bit)=1
CY, fmem.bit
2
2
CY
←
CY
(fmem.bit)
*4
CY, pmem.@L
2
2
CY
←
CY
(pmem
7–2
+L
3–2
.bit(L
1–0
))
*5
CY, @H+mem.bit
2
2
CY
←
CY
(H+mem
3–0
.bit)
*1
CY, fmem.bit
2
2
CY
←
CY
(fmem.bit)
*4
CY, pmem.@L
2
2
CY
←
CY
(pmem
7–2
+L
3–2
.bit(L
1–0
))
*5
CY, @H+mem.bit
2
2
CY
←
CY
(H+mem
3–0
.bit)
*1
CY, fmem.bit
2
2
CY
←
CY
(fmem.bit)
*4
CY, pmem.@L
2
2
CY
←
CY
(pmem
7–2
+L
3–2
.bit(L
1–0
))
*5
CY, @H+mem.bit
2
2
CY
←
CY
(H+mem
3–0
.bit)
*1
addr
—
—
PC
12–0
←
addr
(Optimum instruction is
selected from among BR !addr,
BRCB !caddr and BR $addr by an
assembler.)
PC
12–0
←
addr
*6
!addr
3
3
*6
$addr
1
2
PC
12–0
←
addr
*7
!caddr
2
2
PC
12–0
←
PC
12
+caddr
11–0
*8
PCDE
2
3
PC
12–0
←
PC
12–8
+DE
PCXA
2
3
PC
12–0
←
PC
12–8
+XA
Machine
Cycle
Skip
Condition
Addressing
Area
No. of
Bytes
M
BRCB
B
Note
Instruction Group
Mnemonic
Operands
Operation
Note
SET1
CLR1
SKT
SKF
SKTCLR
AND1
OR1
XOR1
BR
BR