參數(shù)資料
型號(hào)： UPD75108F
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述： 4位單片機(jī)
文件頁(yè)數(shù)： 31/78頁(yè)
文件大?。?/td> 549K
代理商： UPD75108F
31
μ
PD75108F,75112F,75116F
RESET Input in Standby
Mode
Table 8-1 Status of Each Hardware after Resetting
Hardware
Low-order 5 bits of program
memory address 0000H are set
in PC
12
to PC
8
and the contents
of address 0001H are set in PC
7
to PC
0
.
Low-order 6 bits of program
memory address 0000H are set
in PC
13
to PC
8
and the contents
of address 0001H are set in PC
7
to PC
0
.
Held
0
0
Sets program memory address
0000H bit 6 and bit 7 to RBE and
MBE, respectively.
Undefined
Held
*
Held
0, 0
Undefined
0
0
FFH
0
0, 0
Held
0
0
0
Reset (0)
0
0
0, 0
OFF
Clear (0)
0
Undefined
0
0
RESET Input during
Operation
Undefined
0
0
Same as left
Undefined
Undefined
Undefined
0, 0
Undefined
0
0
FFH
0
0, 0
Undefined
0
0
0
Reset (0)
0
0
0, 0
OFF
Clear (0)
0
Undefined
0
0
Carry flag (CY)
Skip flag (SK0 to SK2)
Interrupt status flag (IST0, IST1)
Bank enable flag (MBE, RBE)
Stack pointer (SP)
Data memory (RAM)
General register (X, A, H, L, D, E, B, C)
Bank selection register (MBS, RBS)
PSW
Counter (BT)
Mode register (BTM)
Counter (Tn)
Modulo register (TMODn)
Mode register (TMn)
TOEn, TOFn
Shift register (SIO)
Mode register (SIOM)
Processor clock control register (PCC)
Clock output mode register (CLOM)
Interrupt request flag (IRQ
×××
)
Interrupt enable flag (IE
×××
)
Priority selection register (IPS)
INT0, 1 mode registers (IM0, IM1)
Output buffer
Output latch
I/O mode register (PMGA, B, C)
PTH00 to 03 input latch
Mode register (PTHM)
Bit sequential buffer (BSB0 to BSB3)
Basic interval
timer
Timer/event
counter
(n = 0, 1)
Serial interface
Clock generator,
clock output
circuit
Interrupt
Digital port
Analog port
μ
PD75108F
μ
PD75112F
μ
PD75116F
*
Data of data memory addresses 0F8H to 0FDH becomes undefined by RESET input.
Same as left
Program counter (PC)
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