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參數(shù)資料
| 型號： | UPD75106 |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機(jī) |
| 文件頁數(shù)： | 56/70頁 |
| 文件大?。?/td> | 535K |
| 代理商： | UPD75106 |
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μ
PD75104, 75106, 75108
56
LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE
(T
a
= –40 to +85
°
C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Data Retention Supply
Voltage
Data Retention Supply
Current*
1
Release Signal Set Time
V
DDDR
2.0
6.0
V
I
DDDR
V
DDDR
= 2.0 V
0.1
10
μ
A
t
SREL
0
μ
s
ms
ms
Oscillation Stabilization
Wait Time*
2
t
WAIT
Released by RESET
Released by interrupt request
2
17
/f
X
*
3
*1: The current flowing through internal pull-up resistor, power-ON reset circuit (mask option), and
comparator circuit is not included
2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent
unstable operation when oscillation is started.
3: Depends on the setting of the basic interval timer mode register (BTM) as follows:
BTM3
–
BTM2
0
BTM1
0
BTM0
0
Wait time ( ): f
XX
= 4.19 MHz
2
20
/f
XX
(approx. 250 ms)
2
17
/f
XX
(approx. 31.3 ms)
2
15
/f
XX
(approx. 7.82 ms)
2
13
/f
XX
(approx. 1.95 ms)
–
–
–
0
1
1
1
0
1
1
1
1
DATA RETENTION TIMING (releasing STOP mode by RESET)
STOP mode
Data retention mode
STOP instruction
execution
V
DD
RESET
V
DDDR
t
SREL
t
WAIT
Operation
mode
Internal reset operation
HALT mode
DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)
STOP mode
Data retention mode
STOP instruction execution
V
DD
V
DDDR
t
SREL
t
WAIT
Operation
mode
HALT mode
Standby release signal
(interrupt request)
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