參數(shù)資料
型號(hào)： UPD75104AGC
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述： 4位單片機(jī)
文件頁(yè)數(shù)： 31/66頁(yè)
文件大?。?/td> 460K
代理商： UPD75104AGC
μ
PD75104A, 75108A
31
RESET input during
standby mode
Power-ON Reset or RESET
Input during Operation
Lower 5 bits of program
memory address 0000H are
set to PC
12-8
,*
1
and
contents of address 0001H
are set to PC
7-0
.
Lower 5 bits of program
memory address 0000H
are set to PC
12-8
,*
1
and
contents of address 0001H
are set to PC
7-0
.
Program Counter (PC)
Carry Flag (CY)
Retained
Undefined
Skip Flags (SK0-SK2)
0
0
PSW
Interrupt Status Flags (IST0, IST1)
0
0
Bit 6 of program memory
address 0000H is set in
RBE, and bit 7 is set in
MBE.
Bit 6 of program memory
address 0000H is set in
RBE, and bit 7 is set in
MBE.
Bank Enable Flags (MBE, RBE)
Stack Pointer (SP)
Undefined
Undefined
Data Memory (RAM)
Retained*
2
Undefined
General-Purpose Registers (X,A,H,L,D,E,B,C)
Retained
Undefined
Bank Selector Registers (MBS, RBS)
0, 0
0, 0
Counter (BT)
Undefined
Undefined
Mode Register (BTM)
0
0
Counter (Tn)
0
0
Modulo Register (TMODn)
FFH
FFH
Mode Register (TMn)
0
0
TOEn, TOFn
0, 0
0, 0
Serial Interface
Shift Register (SIO)
Retained
Undefined
Mode Register (SIOM)
0
0
*1: PC
11-8
for
μ
PD75104A
2: Data at data memory addresses 0F8H to 0FDH become undefined when the RESET signal has been input.
Wait*
(31.3 ms: 4.19 MHz)
HALT mode
Operation mode
Operation mode
or standby mode
RESET input
Internal reset operation
Table 8-1 Hardware Device Status After Reset (1/2)
Hardware
Basic interval timer
Timer/Event Counter
(n = 0, 1)
*: The wait time does not include the time required after the
RES
signal has been generated until the
oscillation starts.
Fig. 8-3 Reset by RESET Signal
The status of each internal hardware device after the reset operation has been performed is shown in Table 8-
1.
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