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參數(shù)資料
| 型號： | UPD75068CU |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機 |
| 文件頁數(shù)： | 30/68頁 |
| 文件大小： | 640K |
| 代理商： | UPD75068CU |
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30
μ
PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
RESET input in standby mode
Contents of lower 4 bits of address 0000H
in program memory are set to PC11 - 8,
and that of 0001H are set to PC7 - 0.
Contents of lower 5 bits of address 0000H
in program memory are set to PC12 - 8,
and that of 0001H are set to PC7 - 0.
Retained
0
0
The contents of bit 7 of address 0000H
of the program memory is set to MBE.
Undefined
Retained
Note
Retained
0
Undefined
0
0
FFH
0
0, 0
0
Counter (BT)
Mode register (BTM)
Counter (T0)
Modulo register (TMOD0)
Mode register (TM0)
TOE0, TOUT F/F
Mode register (WM)
Basic interval
timer
Timer/event
counter
Watch timer
8. RESET OPERATION
When the RESET signal is input, the
μ
PD75068 is reset and all hardware is initialized as indicated in Table
8-1. Figure 8-1 shows the reset operation timing.
Figure 8-1. Reset Operation by RESET Input
Table 8-1. Status of All Hardware after Reset (1/2)
RESET input during operation
Same operation as that in
standby state
Same operation as that in
standby state
Undefined
0
0
Same operation as that in
standby state
Undefined
Undefined
Undefined
0
Undefined
0
0
FFH
0
0, 0
0
Note
Data of address 0F8H to 0FDH of the data memory becomes undefined when the RESET signal is input.
Hardware
Program counter (PC)
μ
PD75064
μ
PD75066
μ
PD75068
PSW
Carry flag (CY)
Skip flag (SK0-2)
Interrupt status flag (IST0)
Bank enable flag (MBE)
Stack pointer (SP)
Data memory (RAM)
General purpose register
(X, A, H, L, D, E, B, C)
Bank selection register (MBS)
RESET input
Operation mode or
standby mode
HALT mode
Operation mode
Internal reset operation
Wait
(Approx. 31.3 ms/4.19 MHz)
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