參數(shù)資料
型號(hào)： UPD75068A
廠(chǎng)商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述： 4位單片機(jī)
文件頁(yè)數(shù)： 48/68頁(yè)
文件大?。?/td> 640K
代理商： UPD75068A
48
μ
PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
SBI Mode (SCK ... Internal clock output (Master))
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
V
DD
= 4.5 to 6.0 V
1600
ns
t
KCY3
3800
ns
SCK high- and low-level
width
V
DD
= 4.5 to 6.0 V
t
KCY3
/2-50
ns
t
KCY3
/2-150
ns
SB0, 1 setup time
(to SCK
↑
)
SB0, 1 hold time
(from SCK
↑
)
SB0, 1 output
delay time from
SCK
↓
V
DD
= 4.5 to 6.0 V
0
250
ns
t
KSO3
0
1000
ns
SB0, 1
↓
from SCK
↑
t
KSB
t
KCY3
ns
SCK
↓
from SB0, 1
↓
t
SBK
t
KCY3
ns
SB0, 1 low-level width
t
SBL
t
KCY3
ns
SB0, 1 high-level width
t
SBH
t
KCY3
ns
SBI Mode (SCK ... External clock input (Slave))
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
V
DD
= 4.5 to 6.0 V
800
ns
t
KCY4
3200
ns
SCK high- and low-level
width
V
DD
= 4.5 to 6.0 V
400
ns
1600
ns
SB0, 1 setup time
(to SCK
↑
)
SB0, 1 hold time
(from SCK
↑
)
SB0, 1 output
delay time from
SCK
↓
V
DD
= 4.5 to 6.0 V
0
300
ns
t
KSO4
0
1000
ns
SB0, 1
↓
from SCK
↑
t
KSB
t
KCY4
ns
SCK
↓
from SB0, 1
↑
t
SBK
t
KCY4
ns
SB0, 1 low-level width
t
SBL
t
KCY4
ns
SB0, 1 high-level width
t
SBH
t
KCY4
ns
Note
R
L
and C
L
are load resistance and load capacitance, respectively, for the SB0 and SB1 output lines.
t
KSI4
t
KCY4
/2
ns
t
SIK3
150
ns
t
KSI3
t
KCY3
/2
ns
t
SIK4
100
ns
R
L
= 1 k
,
C
L
= 100 pF
Note
t
KL4
t
KH4
R
L
= 1 k
,
C
L
= 100 pF
Note
t
KL3
t
KH3
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