44
μ
PD75048
Ma-
chine
Cyc-
les
—
Ad-
dress-
ing
Area
*6
Instruc-
tions
Mne-
monics
Operand
Bytes
Operation
Skip
Conditions
Branch
BR
addr
—
PC
12-0
←
addr
(The most suitable instruction
is selectable from among BR
!addr, BRCB !caddr, and BR
$addr depending on the
assembler.)
PC
12-0
←
addr
PC
12-0
←
addr
PC
12-0
←
PC
12
+ caddr
11-0
(SP-4)(SP-1)(SP-2)
←
PC
11-0
(SP-3)
←
MBE,0, 0, PC
12
PC
12-0
←
addr,SP
←
SP-4
(SP-4)(SP-1)(SP-2)
←
PC
11-0
(SP-3)
←
MBE,0, 0, PC
12
PC
12-0
←
00,faddr,SP
←
SP-4
MBE,x,x,PC
12
←
(SP+1)
PC
11-0
←
(SP)(SP+3)(SP+2)
SP
←
SP+4
MBE,x,x,PC
12
←
(SP+1)
PC
11-0
←
(SP)(SP+3)(SP+2)
SP
←
SP+4,
then skip unconditionally
MBE,x,x,PC
12
←
(SP+1)
PC
11-0
←
(SP)(SP+3)(SP+2)
PSW
←
(SP+4)(SP+5), SP
←
SP+6
(SP-1)(SP-2)
←
rp, SP
←
SP-2
(SP-1)
←
MBS,(SP-2)
←
0,SP
←
SP-2
rp
←
(SP+1)(SP),SP
←
SP+2
MBS
←
(SP+1),SP
←
SP+2
IME
←
1
IExxx
←
1
IME
←
0
IExxx
←
0
A
←
PORT
n
XA
←
PORT
n+1
,PORT
n
PORT
n
←
A
PORT
n+1
,PORT
n
←
XA
Set HALT Mode(PCC.2
←
1)
Set STOP Mode (PCC.3
←
1)
No Operation
MBS
←
n(n=0, 1, 4, 5, 6, 7, 15)
.Where TBR instruction,
PC
12-0
←
(taddr)
4-0
+(taddr+1)
.Where TCALL instruction,
(SP-4)(SP-1)(SP-2)
←
PC
11-0
(SP-3)
←
MBE, 0, 0, PC
12
PC
12-0
←
(taddr)
4-0
+(taddr+1)
SP
←
SP-4
.Except for TBR and TCALL
instructions,
Instruction execution of
(taddr)(taddr+1)
!addr
$addr
!caddr
!addr
3
1
2
3
3
2
2
3
*6
*7
*8
*6
BRCB
CALL
Subrou-
tine/
Stack
Control
CALLF
!faddr
2
2
*9
RET
1
3
RETS
1
3+S
Unconditional
RETI
1
3
PUSH
rp
BS
rp
BS
1
2
1
2
1
2
1
2
POP
Inter-
rupt
Control
EI
2
2
2
2
2
2
2
2
IExxx
DI
IExxx
I/O
IN
A,PORTn
XA,PORTn
PORTn,A
PORTn,XA
2
2
2
2
2
2
2
2
(n = 0-11)
(n = 4, 6)
OUT
(n = 2-10)
(n = 4, 6)
CPU
Control
HALT
STOP
NOP
SEL
2
2
1
2
2
2
1
2
Special
MBn
GETI
taddr
1
3
*10
Depends on
referenced
instruction
Note : When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15.
Remarks : TBR and TCALL instructions are assembler seudo-instructions for the table definition of
GETI instruction.
#