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參數(shù)資料
| 型號： | UPD75048 |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機 |
| 文件頁數(shù)： | 23/68頁 |
| 文件大小： | 538K |
| 代理商： | UPD75048 |
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23
μ
PD75048
V
DD
I
XT1
V
DD
XT2
X1
X2
Subsystem
clock
oscillator
Main system
clock
oscillator
Watch timer
f
XT
f
X
1/2 to 1/4096
Frequency divider
1/2 1/16
Multi-function timer
Basic interval timer (BT)
Timer/event counter
Serial interface
Watch timer
A/D converter
(successive approximation)
INT0 noise rejecter circuit
Clock output circuit
.
.
.
.
.
.
.
.
S
S
Frequency
divider
CPU
INT0 noise
rejecter circuit
Clock output
circuit
.
.
.
WM.3
SCC
Oscillator
disable
signal
SCC3
SCC0
PCC0
PCC1
PCC2
PCC3
4
HALT*
STOP*
PCC2, PCC3
clear signal
STOP F/F
Q
S
R
HALT F/F
S
R
Q
Wait release
signal from BT
RESET signal
Standby release
signal from interrupt
control circuit
1/4
Φ
PCC
Remarks
1: f
X
= Main system clock frequency
2: f
= Subsystem clock frequency
3:
Φ =
CPU clock
4: PCC: Processor clock control register
5: SCC:System clock control register
6: * indicates instruction execution.
7: One clock cysle (t
CY
) of
Φ
is one machine cycle of an instruction. For t
CY
, refer to AC
characteristics in 11. ELECTRICAL SPECIFICATIONS.
Fig. 6-1 Clock Generator Block Diagram
6.2
CLOCK GENERATOR CIRCUIT
The operation of the clock generator circuit is determined by the processor clock control regiser (PPC)
and system clock control register (SCC).
This circuit can generate two types of clocks: main system clock and subsystem clock.
In addition, it can also change the instruction execution time.
0.95
μ
s, 1.91
μ
s, 15.3
μ
s (main system clock: 4.19 MHz)
122
μ
s (subsystem clock: 32.768 kHz)
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