μ
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
60
Data Sheet U10165EJ2V0DS00
DC Characteristics (T
A
= –40 to +85C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Supply current
Note 1
I
DD1
V
DD
= 5.0 V
±
10%
Note 3
V
DD
= 3.0 V
±
10%
Note 4
V
DD
= 5.0 V
±
10%
mode
V
DD
= 3.0 V
±
10%
V
DD
= 5.0 V
±
10%
Note 3
V
DD
= 3.0 V
±
10%
Note 4
HALT
V
DD
= 5.0 V
±
10%
V
DD
= 3.0 V
±
10%
V
DD
= 3.0 V
±
10%
voltage
V
DD
= 2.0 V
±
10%
2.2
6.6
mA
0.48
1.5
mA
I
DD2
HALT
0.86
2.6
mA
0.43
1.3
mA
I
DD1
1.7
4.5
mA
0.4
1.2
mA
I
DD2
0.7
2
mA
mode
0.39
1.2
mA
I
DD3
Low-
11
33
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
5.5
17
mode
Note 6
dissipation
mode
V
DD
= 3.0 V, T
A
= 25C
11
22
V
DD
= 3.0 V
±
10%
V
DD
= 3.0 V, T
A
= 25C
9.2
27
9.2
18
I
DD4
HALT
Low-
V
DD
= 3.0 V
±
10%
6.4
20
mode
voltage
V
DD
= 2.0 V
±
10%
2.5
8
mode
Note 6
V
DD
= 3.0 V, T
A
= 25C
Low current
dissipation
mode
6.4
12.8
V
DD
= 3.0 V
±
10%
4.6
13.8
V
DD
= 3.0 V, T
A
= 25C
4.6
9.2
I
DD5
XT1 =
V
DD
= 5.0 V
±
10%
V
DD
= 3.0 V
±
10%
0.05
10
0 V
Note 8
0.02
5
STOP mode
T
A
= 25C
0.02
3
Notes 1.
The current flowing to the internal pull-up resistor is not included.
Including the case when the subsystem clock oscillates.
When the device operates in high-speed mode with the processor clock control register (PCC) set to
0011.
When the device operates in low-speed mode with PCC set to 0000.
When the device operates on the subsystem clock, with the system clock control register (SCC) set
to 1001 and oscillation of the main system clock stopped.
When the sub-oscillation circuit control register (SOS) is set to 0000.
When SOS is set to 0010.
When SOS is set to 00
×
1, and the sub-oscillation circuit feedback resistor is not used (
×:
don’t care).
2.
3.
4.
5.
6.
7.
8.
6.0-MHz
Note 2
crystal
oscillation
C1 = C2
= 22 pF
4.19-MHz
Note 2
crystal
oscillation
C1 = C2
= 22 pF
32.768-
kHz
Note 5
crystal
oscillation