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參數(shù)資料
| 型號(hào)： | uPD750066GT |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 4位單晶片微控制器 |
| 文件頁(yè)數(shù)： | 57/82頁(yè) |
| 文件大?。?/td> | 460K |
| 代理商： | UPD750066GT |
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57
μ
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Data Sheet U10165EJ2V0DS00
XT1
XT2
Subsystem Clock Oscillator Characteristics (T
A
= –40 to +85C, V
DD
= 1.8 to 5.5 V)
Resonator
Recommended
Constants
Parameter
Conditions
MIN.
TYP.
MAX.
Unit
Crystal
resonator
Oscillation frequency
(f
XT
)
Note 1
32
32.768
35
kHz
Oscillation
stabilization time
Note 2
V
DD
= 4.5 to 5.5 V
1.0
2
s
10
External
clock
XT1 input frequency
(f
XT
)
Note 1
32
100
kHz
XT1 input high-/
low-level width
(t
XTH
, t
XTL
)
5
15
μ
s
Notes 1.
The oscillation frequency and XT1 input frequency shown above indicate only oscillator characteristics.
Refer to AC Characteristics for instruction execution time.
The oscillation stabilization time is the time required to stabilize oscillation after V
DD
has been applied.
2.
Caution When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figure to avoid an adverse effect from wiring capacitance.
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as V
SS
.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
XT1
XT2
C3
C4
R
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