參數(shù)資料
型號: uPD750066CU
廠商: NEC Corp.
英文描述: 4-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: 4位單晶片微控制器
文件頁數(shù): 62/82頁
文件大?。?/td> 460K
代理商: UPD750066CU
μ
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
62
Data Sheet U10165EJ2V0DS00
Note 2
Note 2
Serial transfer operation
2-wire and 3-wire serial I/O modes (SCK ··· internal clock output): (T
A
= –40 to +85C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
t
KCY1
V
DD
= 2.7 to 5.5 V
1300
ns
3800
ns
SCK high-/low-level width
t
KL1
,
V
DD
= 2.7 to 5.5 V
t
KCY1
/2–50
ns
t
KH1
t
KCY1
/2–150
ns
SI
Note 1
setup time (to SCK
)
t
SIK1
V
DD
= 2.7 to 5.5 V
150
ns
500
ns
SI
Note 1
hold time
t
KSI1
V
DD
= 2.7 to 5.5 V
400
ns
(from SCK
)
SCK
SO
Note 1
output
600
ns
t
KSO1
R
L
= 1 k
,
V
DD
= 2.7 to 5.5 V
0
250
ns
delay time
C
L
= 100 pF
0
1000
ns
Notes 1.
Read as SB0 or SB1 when using the 2-wire serial I/O mode.
R
L
and C
L
are the load resistance and load capacitance of the SO output line.
2.
2-wire and 3-wire serial I/O modes (SCK ··· external clock input): (T
A
= –40 to +85C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
t
KCY2
V
DD
= 2.7 to 5.5 V
800
ns
3200
ns
SCK high-/low-level width
t
KL2
,
V
DD
= 2.7 to 5.5 V
400
ns
t
KH2
1600
ns
SI
Note 1
setup time (to SCK
)
t
SIK2
V
DD
= 2.7 to 5.5 V
100
ns
150
ns
SI
Note 1
hold time
t
KSI2
V
DD
= 2.7 to 5.5 V
400
ns
(from SCK
)
SCK
SO
Note 1
output
600
ns
t
KSO2
R
L
= 1 k
,
V
DD
= 2.7 to 5.5 V
0
300
ns
delay time
C
L
= 100 pF
0
1000
ns
Notes 1.
Read as SB0 or SB1 when using the 2-wire serial I/O mode.
R
L
and C
L
are the load resistance and load capacitance of the SO output line.
2.
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