參數(shù)資料
型號： uPD750064CUA
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 4位單晶片微控制器
文件頁數(shù)： 37/82頁
文件大?。?/td> 460K
代理商： UPD750064CUA
37
μ
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Data Sheet U10165EJ2V0DS00
8. STANDBY FUNCTION
In order to save power dissipation while a program is in a standby mode, two types of standby modes (STOP
mode and HALT mode) are provided for the
μ
PD750068.
Table 8-1. Operation Status in Standby Mode
Mode
STOP Mode
HALT Mode
Item
Set instruction
STOP instruction
HALT instruction
System clock when set
Settable only when the main system
clock is used.
Settable both by the main system clock
and subsystem clock.
Operation
status
Clock generator
The main system clock stops oscillation.
Only the CPU clock
Φ
halts (oscillation
continues).
Basic interval timer/
watchdog timer
Operation stops.
Operable only when the main system
clock is oscillated (The IRQBT is set in
the reference time interval).
Serial interface
Operable only when an external SCK
input is selected as the serial clock.
Operable only when an external SCK
input is selected as the serial clock or
when the main system clock is oscillated.
Timer/event counter
Operable only when a signal input to
the TI0 and TI1 pins or a watch timer
which selected f
XT
is specified as the
count clock.
Operable only when a signal input to
the TI0 and TI1 pins or a watch timer
which selected f
XT
is specified as the
count clock or when the main system
clock is oscillated.
Watch timer
Operable when f
XT
is selected as the
count clock.
Operable.
A/D converter
Operation stops.
Operable only when the main system
clock is oscillated.
External interrupt
The INT1, 2, and 4 are operable.
Only the INT0 is not operated
Note
.
CPU
Operation stops.
Release signal
Interrupt request signal sent from the operable hardware enabled by the interrupt
enable flag.
Test request signal sent from the test source enabled by the test enable flag
RESET signal generation
Note
Can operate only when the noise elimination circuit is not used (IM02 = 1) by bit 2 of the edge detection
mode register (IM0).
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