參數(shù)資料
型號(hào)： uPD750064CU
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 4位單晶片微控制器
文件頁(yè)數(shù)： 61/82頁(yè)
文件大?。?/td> 460K
代理商： UPD750064CU
61
μ
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Data Sheet U10165EJ2V0DS00
AC Characteristics (T
A
= –40 to +85C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
CPU clock cycle time
Note 1
t
CY
Operates with
V
DD
= 2.7 to 5.5 V
0.67
64
μ
s
μ
s
μ
s
(minimum instruction
main system clock
0.95
64
execution time = 1
Operates with
114
122
125
machine cycle)
subsystem clock
TI0, TI1 input frequency
f
TI
V
DD
= 2.7 to 5.5 V
0
1.0
MHz
0
275
kHz
TI0, TI1 input high-/low-level
t
TIH
, t
TIL
V
DD
= 2.7 to 5.5 V
0.48
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
width
1.8
Interrupt input high-/
t
INTH
, t
INTL
INT0
IM02 = 0
Note 2
low-level width
IM02 = 1
10
INT1, 2, 4
10
KR0 to 3
10
RESET low-level width
t
RSL
10
Notes 1.
The cycle time (minimum instruction
execution time) of the CPU clock (
Φ
)
is determined by the oscillation frequency
of the connected resonator (and external
clock), the system clock control register
(SCC), and processor clock control
register (PCC).
The figure on the right shows the supply
voltage V
DD
vs. cycle time t
CY
characteristics when the device operates
with the main system clock.
2t
CY
or 128/f
X
depending on the setting
of the interrupt mode register (IM0).
2.
0
1
2
3
4
5
6
1
0.5
2
3
4
5
6
60
64
(with main system clock)
t
CY
vs V
DD
Guaranteed operation range
C
C
μ
Supply voltage V
DD
[V]
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