參數(shù)資料
型號: UPD750004CU
廠商: NEC Corp.
英文描述: 4 BIT SINGLE-CHIP MICROCONTROLLER
中文描述: 4位單片機
文件頁數(shù): 60/84頁
文件大小: 719K
代理商: UPD750004CU
60
μ
PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)
AC CHARACTERISTICS (T
A
= -40 to +85
°
C, V
DD
= 2.2 to 5.5 V)
CPU clock cycle
time
Note 1
(minimum
instruction execution time
= 1 machine cycle)
TI0 input frequency
TI0 input high/low level
width
Interrupt input high/low
level width
RESET low level width
V
DD
= 2.7 to 5.5 V
V
DD
= 1.8 to 5.5 V
V
DD
= 2.7 to 5.5 V
Remark
The shaded portion is guaranteed only when the
external clock is used.
When external
clock is used
IM02 = 0
IM02 = 1
Notes 1.
The cycle time of the CPU clock (
Φ
)
(minimum instruction execution time) de-
pends on the frequency of connected reso-
nator (and external clock), the system
clock control register (SCC), and the proc-
essor clock control register (PCC).
The figure on the right side shows the
cycle time t
CY
characteristics for the sup-
ply voltage V
DD
during main system clock
operation.
2.
This value becomes 2t
CY
or 128/f
X
accord-
ing to the setting of the interrupt mode
register (IM0).
When ceramic
or crystal is
used
Operated
by main
system
clock
pulse
t
CY
f
TI
t
TIH
,
t
TIL
t
INTH
,
t
INTL
t
RSL
Conditions
Min.
Typ.
Max.
Unit
0.67
64
μ
s
0.85
64
μ
s
0.67
64
μ
s
0.95
64
μ
s
Operated by subsystem clock pulse
114
122
125
μ
s
V
DD
= 2.7 to 5.5 V
0
1.0
MHz
0
275
kHz
V
DD
= 2.7 to 5.5 V
0.48
μ
s
1.8
μ
s
INT0
Note 2
μ
s
10
μ
s
INT1, INT2, and INT4
10
μ
s
KR0 to KR7
10
μ
s
10
μ
s
Parameter
Symbol
0
1
2
3
4
5
6
0.5
1
2
3
4
5
6
60
64
t
CY
vs. V
DD
(Main system clock in operation)
Operation guaranteed
range
1.8
2.2 2.7
Power supply voltage V
DD
[V]
5.5
0.67
0.95
0.85
C
C
μ
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