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參數資料
| 型號： | UPD750004 |
| 廠商： | NEC Corp. |
| 英文描述： | 4 BIT SINGLE-CHIP MICROCONTROLLER |
| 中文描述： | 4位單片機 |
| 文件頁數： | 55/84頁 |
| 文件大?。?/td> | 719K |
| 代理商： | UPD750004 |
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55
μ
PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)
Recommended
constant
Resonator
Parameter
kHz
s
s
kHz
μ
s
Unit
Max.
Typ.
Min.
35
2
10
100
15
32.768
1.0
32
32
5
Conditions
Crystal
External
clock
XT1
XT2
Oscillator frequency (f
XT
)
Note 1
Oscillation settling time
Note 2
XT1 input frequency (f
XT
)
Note 1
XT1 input high/low level width
(t
XTH
, t
XTL
)
V
DD
= 2.2 to 5.5 V
V
DD
= 4.5 to 5.5 V
V
DD
= 2.2 to 5.5 V
V
DD
= 1.8 to 5.5 V
V
DD
= 1.8 to 5.5 V
CHARACTERISTICS OF THE SUBSYSTEM CLOCK OSCILLATOR (T
A
= -40 to +85
°
C)
Notes 1.
The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item of
AC characteristics for the instruction execution time.
2.
The oscillation settling time means the time required for the oscillation to settle after V
DD
is applied.
Caution When the subsystem clock oscillator is used, conform to the following guidelines when wiring at
the portions of surrounded by dotted lines in the figures above to eliminate the influence of the
wiring capacity.
The wiring must be as short as possible.
Other signal lines must not run in these areas.
Any line carrying a high fluctuating current must be kept away as far as possible.
The grounding point of the capacitor of the oscillator must have the same potential as that of V
SS
It must not be grounded to ground patterns carrying a large current.
No signal must be taken from the oscillator.
When the subsystem clock is used, pay special attention to its wiring; the subsystem clock
oscillator has low amplification to minimize current consumption and is more likely to malfunction
due to noise than the main system clock oscillator.
C3
C4
R
XT1
XT2
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