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參數(shù)資料
| 型號： | UPD72871FA2 |
| 廠商： | NEC Corp. |
| 英文描述： | IEEE1394 1-CHIP OHCI HOST CONTROLLER |
| 中文描述： | IEEE1394連接1 - OHCI主機控制器芯片 |
| 文件頁數(shù)： | 20/48頁 |
| 文件大?。?/td> | 311K |
| 代理商： | UPD72871FA2 |
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Preliminary Data Sheet S13925EJ2V0DS00
20
μ
PD72870,72871
Table
2-1. Bit Field Description (3/3)
Field
Size
R/W
Reset value
Description
Port_event
1
R/W
0
Set to 1 when the Int_Enable bit in the register map of each port is 1 and
there is a change in the ports connected, Bias, Disabled and Fault bits.
Set to 1 when the Resume_int bit is 1 and any one port does resume.
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
Enab_accel
1
R/W
0
Enables arbitration acceleration.
Ack-acceleration and Fly-by arbitration are enabled.
1: Enabled
0: Disabled
If this bit changes while the bus request is pending, the operation is not
guaranteed.
Enab_multi
1
R/W
0
Enable multi-speed packet concatenation.
Setting this bit to 1 follows multi-speed transmission.
When this bit is set to 0,the packet will be transmitted with the same speed
as the first packet.
Page_select
3
R/W
000
Select page address between 1000 to 1111.
000: Port Status Page
001: Vendor Definition Page
Others: Unused
Port Selection.
Selecting 000 (Port Status Page) with the page selection selects the port.
μ
PD72870
μ
PD72871
Port_select
4
R/W
0000
0000: Port 0
0001: Port 1
0010: Port 2
Others: Unused
0000: Port 0
Others: Unused
Reserved
-
R
000…
Reserved. Read as 0.
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