- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379501 > UPD720101 (NEC Corp.) USB2.0 HOST CONTROLLER PDF資料下載
參數(shù)資料
| 型號： | UPD720101 |
| 廠商： | NEC Corp. |
| 英文描述： | USB2.0 HOST CONTROLLER |
| 中文描述： | USB2.0主機(jī)控制器 |
| 文件頁數(shù)： | 1/36頁 |
| 文件大?。?/td> | 406K |
| 代理商： | UPD720101 |
當(dāng)前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
MOS INTEGRATED CIRCUIT
μ
PD720101
USB2.0 HOST CONTROLLER
Document No.
Date Published June 2004 NS CP (N)
Printed in Japan
S16265EJ4V0DS00 (4th edition)
DATA SHEET
The mark shows major revised points.
2002
The
μ
PD720101 complies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller
Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for
high-speed signaling and works up to 480 Mbps. The
μ
PD720101 is integrated 3 host controller cores with PCI
interface and USB2.0 transceivers into a single chip.
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.
μ
PD720101 User’s Manual: S16336E
FEATURES
Compliant with Universal Serial Bus Specification Revision 2.0 (Data rate 1.5/12/480 Mbps)
Compliant with Open Host Controller Interface Specification for USB Rev 1.0a
Compliant with Enhanced Host Controller Interface Specification for USB Rev 1.0
PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI host
controller core for high-speed signaling.
Root hub with 5 (max.) downstream facing ports which are shared by OHCI and EHCI host controller cores.
All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps)
transaction.
Configurable number of downstream facing ports (2 to 5)
32-bit 33 MHz host interface compliant to PCI Specification release 2.2
Supports PCI Mobile Design Guide Revision 1.1
Supports PCI-Bus Power Management Interface Specification release 1.1
PCI bus bus-master access
System clock is generated by 30 MHz X’tal or 48 MHz clock input.
System clock frequency should be set from system software (BIOS) or EEPROM. More detail, see
μ
PD720101
User’s Manual.
Operational registers direct-mapped to PCI memory space
Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard
implementation.
3.3 V power supply, PCI signal pins have 5 V tolerant circuit.
ORDERING INFORMATION
Part Number
Package
μ
PD720101GJ-UEN
144-pin plastic LQFP (Fine pitch) (20
×
20)
μ
PD720101F1-EA8
144-pin plastic FBGA (12
×
12)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD720101F1-EA8 | USB2.0 HOST CONTROLLER |
| UPD720102 | PRELIMINARY PRODUCT BRIEF, USB 2.0 HOST CONTROLLER |
| UPD72012GB-003 | HUB CONTROLLER FOR UNIVERSAL SERIAL BUS |
| UPD720012 | HUB CONTROLLER FOR UNIVERSAL SERIAL BUS |
| UPD72012CU | HUB CONTROLLER FOR UNIVERSAL SERIAL BUS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD720101F1 | 制造商:NEC Electronics Corporation 功能描述: |
| UPD720101F1-EA8 | 制造商:NEC Electronics Corporation 功能描述: |
| UPD720101F1-EA8 ( PRICE BREAK 250K - | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD720101F1-EA8_NEC | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD720101F1-EA8-A | 功能描述:HOST CTLR USB 2.0 144-FBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:2,450 系列:- 控制器類型:SPI 總線至 I²C 總線橋接 接口:I²C，串行，SPI 電源電壓:2.4 V ~ 3.6 V 電流 - 電源:11mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-HVQFN（4x4） 包裝:托盤 配用:568-3511-ND - DEMO BOARD SPI TO I2C 其它名稱:935286452157SC18IS600IBSSC18IS600IBS-ND |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。