I2CX
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� UPD70F3714GC-8BS-A
寤犲晢锛� Renesas Electronics America
鏂囦欢闋佹暩(sh霉)锛� 85/320闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� MCU 32BIT V850ES/LX2 64-LQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 300
绯诲垪锛� V850ES/Ix2
鏍稿績铏曠悊鍣細 V850ES
鑺珨灏哄锛� 32-浣�
閫熷害锛� 20MHz
閫i€氭€э細 CSI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 LVD锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 39
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 128KB锛�128K x 8锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 6K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 3.5 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x10b
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 64-LQFP
鍖呰锛� 鎵樼洡
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2011-2012 Microchip Technology Inc.
Preliminary
DS61168D-page 175
PIC32MX1XX/2XX
REGISTER 17-1:
I2CXCON: I2C CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0
鈥�
23:16
U-0
鈥�
15:8
R/W-0
U-0
R/W-0
R/W-1, HC
R/W-0
ON(1)
鈥�
SIDL
SCLREL
STRICT
A10M
DISSLW
SMEN
7:0
R/W-0
R/W-0, HC
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
Legend:
HC = Cleared in Hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 鈥�0鈥�
-n = Value at POR
鈥�1鈥� = Bit is set
鈥�0鈥� = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as 鈥�0鈥�
bit 15
ON: I2C Enable bit(1)
1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins
0 = Disables the I2C module; all I2C pins are controlled by PORT functions
bit 14
Unimplemented: Read as 鈥�0鈥�
bit 13
SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12
SCLREL: SCLx Release Control bit (when operating as I2C slave)
1 = Release SCLx clock
0 = Hold SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software can write 鈥�0鈥� to initiate stretch and write 鈥�1鈥� to release clock). Hardware clear at
beginning of slave transmission. Hardware clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software can only write 鈥�1鈥� to release clock). Hardware clear at beginning of slave
transmission.
bit 11
STRICT: Strict I2C Reserved Address Rule Enable bit
1 = Strict reserved addressing is enforced. Device does not respond to reserved address space or generate
addresses in reserved address space.
0 = Strict I2C Reserved Address Rule not enabled
bit 10
A10M: 10-bit Slave Address bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
bit 9
DISSLW: Disable Slew Rate Control bit
1 = Slew rate control disabled
0 = Slew rate control enabled
bit 8
SMEN: SMBus Input Levels bit
1 = Enable I/O pin thresholds compliant with SMBus specification
0 = Disable SMBus input thresholds
Note 1: When using 1:1 PBCLK divisor, the user鈥檚 software should not read/write the peripheral鈥檚 SFRs in the
SYSCLK cycle immediately following the instruction that clears the module鈥檚 ON bit.
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