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參數(shù)資料
| 型號(hào)： | UPD70F3033AY |
| 廠商： | NEC Corp. |
| 英文描述： | V850/SB1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | V850/SB1TM 32-/16-BIT單晶片微控制器 |
| 文件頁數(shù)： | 32/56頁 |
| 文件大小： | 357K |
| 代理商： | UPD70F3033AY |
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Data Sheet U14734EJ1V0DS00
32
μ
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(4) Bus timing
(a) Clock asynchronous (T
A
= –40 to +85°C, V
DD
= BV
DD
= 4.0 to 5.5 V, V
SS
= BV
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address setup time (to ASTB
↓
)
<10>
t
SAST
0.5T
– 16
ns
Address hold time (from ASTB
↓
)
<11>
t
HSTA
0.5T
– 15
ns
Address float from DSTB
↓
<12>
t
FDA
0
ns
Data input setup time from address
<13>
t
SAID
(2 + n)T – 40
ns
Data input setup time from DSTB
↓
<14>
t
SDID
(1 + n)T – 40
ns
Delay time from ASTB
↓
to DSTB
↓
<15>
t
DSTD
0.5T
– 15
ns
Data input hold time (from DSTB
↑
)
<16>
t
HDID
0
ns
Address output time from DSTB
↑
<17>
t
DDA
(1 + i)T – 15
ns
Delay time from DSTB
↑
to ASTB
↑
<18>
t
DDST1
0.5T – 15
ns
Delay time from DSTB
↑
to ASTB
↓
<19>
t
DDST2
(1.5 + i)T – 15
ns
DSTB low-level width
<20>
t
WDL
(1 + n)T – 22
ns
ASTB high-level width
<21>
t
WSTH
T – 15
ns
Data output time from DSTB
↓
<22>
t
DDOD
10
ns
Data output setup time (to DSTB
↑
)
<23>
t
SODD
(1 + n)T – 25
ns
Data output hold time (from DSTB
↑
)
<24>
t
HDOD
T – 20
ns
<25>
t
SAWT1
n
≥
1
1.5T – 40
ns
WAIT setup time (to address)
<26>
t
SAWT2
n
≥
1
(1.5 + n)T – 40
ns
<27>
t
HAWT1
n
≥
1
(0.5 + n)T
ns
WAIT hold time (from address)
<28>
t
HAWT2
n
≥
1
(1.5 + n)T
ns
<29>
t
SSTWT1
n
≥
1
T – 32
ns
WAIT setup time (to ASTB
↓
)
<30>
t
SSTWT2
n
≥
1
(1 + n)T – 32
ns
<31>
t
HSTWT1
n
≥
1
nT
ns
WAIT hold time (from ASTB
↓
)
<32>
t
HSTWT2
n
≥
1
(1 + n)T
ns
HLDRQ high-level width
<33>
t
WHQH
T + 10
ns
HLDAK low-level width
<34>
t
WHAL
T – 15
ns
Bus output delay time from HLDAK
↑
<35>
t
DHAC
–6
ns
Delay time from HLDRQ
↓
to HLDAK
↓
<36>
t
DHQHA1
(2n + 7.5)T + 25
ns
Delay time from HLDRQ
↑
to HLDAK
↑
<37>
t
DHQHA2
0.5T
1.5T + 25
ns
Remarks 1.
T = 1/f
CPU
(f
CPU
: CPU clock frequency)
n: Number of wait clocks inserted in the bus cycle.
The sampling timing changes when a programmable wait is inserted.
The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from
X1.
2.
3.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD703031A | V850/SB1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS |
| UPD703031AGC | V850/SB1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS |
| UPD703031AGF | V850/SB1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS |
| UPD703031AY | V850/SB1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS |
| UPD703033A | V850/SB1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD70F3033AYGC-8EU | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD70F3033AYGC-8EU-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD70F3033AYGF-3BA | 制造商:NEC 制造商全稱:NEC 功能描述:V850/SB1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS |
| UPD70F3033AYGF-3BA-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD70F3033AYGF-8EU | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
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