參數資料
型號: UPD70F3003A
廠商: NEC Corp.
英文描述: V853TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER
中文描述: V853TM 32-/16-BIT單片機
文件頁數: 26/44頁
文件大?。?/td> 295K
代理商: UPD70F3003A
μ
PD70F3003A, 70F3025A
26
Data Sheet U13189EJ3V0DS00
(7) Bus hold timing (1/2)
Parameter
Symbol
Condition
25 MHz Model
33 MHz Model
Unit
MIN.
MAX.
MIN.
MAX.
HLDRQ setup time (vs. CLKOUT
)
<54>
t
SHOK
5
5
ns
HLDRQ hold time (vs. CLKOUT
)
<55>
t
HKHQ
5
5
ns
CLKOUT
↑→
HLDAK delay time
<56>
t
DKHA
20
20
ns
HLDRQ width, high
<57>
t
WHQH
T + 10
T + 10
ns
HLDAK width, low
<58>
t
WHAL
–40
°
C
T
A
+70
°
C
T – 10
T – 10
ns
70
°
C
<
T
A
85
°
C
T – 12
T – 12
ns
CLKOUT
Bus float delay time
<59>
t
DKF
20
20
ns
HLDAK
↑→
bus output delay time
<60>
t
DHAC
–3
–3
ns
HLDRQ
↓→
HLDAK
delay time
<61>
t
DHQHA1
(2 n + 7.5) T + 20
(2 n + 7.5) T + 20
ns
HLDRQ
↑→
HLDAK
delay time
<62>
t
DHQHA2
0.5 T
1.5 T + 20
0.5 T
1.5 T + 20
ns
Remarks 1.
T = t
CYK
2.
n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when
the programmable wait state is inserted.
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