
CHAPTER 26 ELECTRICAL SPECIFICATIONS
User
’
s Manual U15862EJ3V0UD
732
CSI0 Timing
(1) Master mode
(T
A
=
40 to
+
85
°
C, V
DD
= EV
DD
= AV
REF0
= 2.7 to 5.5 V, 2.7 V
≤
BV
DD
≤
V
DD
, 2.7 V
≤
AV
REF1
≤
V
DD
, V
SS
= EV
SS
=
BV
SS
= AV
SS
= 0 V, C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
REGC = V
DD
= 4.0 to 5.5 V
200
ns
SCK0n cycle time
t
KCY1
<99>
REGC = Capacity, V
DD
= 4.0 to 5.5 V,
REGC = V
DD
= 2.7 to 5.5 V
400
ns
SCK0n high-/low-level width
t
KH1
, t
KL1
<100>
t
KCY1
/2
–
30
ns
REGC = V
DD
= 4.0 to 5.5 V
30
ns
SI0n setup time (to SCK0n
↑
)
t
SIK1
<101>
REGC = Capacity, V
DD
= 4.0 to 5.5 V,
REGC = V
DD
= 2.7 to 5.5 V
50
ns
REGC = V
DD
= 5 V
±
10%
30
ns
SI0n hold time (from SCK0n
↑
)
t
KSI1
<102>
REGC = Capacity, V
DD
= 4.0 to 5.5 V,
REGC = V
DD
= 2.7 to 5.5 V
50
ns
REGC = V
DD
= 4.0 to 5.5 V
30
ns
Delay time from SCK0n
↓
to SO0n
output
t
KSO1
<103>
REGC = Capacity, V
DD
= 4.0 to 5.5 V,
REGC = V
DD
= 2.7 to 5.5 V
60
ns
Remark
n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)
(2) Slave mode
(T
A
=
40 to
+
85
°
C, V
DD
= EV
DD
= AV
REF0
= 2.7 to 5.5 V, 2.7 V
≤
BV
DD
≤
V
DD
, 2.7 V
≤
AV
REF1
≤
V
DD
, V
SS
= EV
SS
=
BV
SS
= AV
SS
= 0 V, C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
SCK0n cycle time
REGC = V
DD
= 4.0 to 5.5 V
200
ns
t
KCY2
<99>
REGC = Capacity, V
DD
= 4.0 to 5.5 V,
REGC = V
DD
= 2.7 to 5.5 V
400
ns
REGC = V
DD
= 4.0 to 5.5 V
45
ns
SCK0n high-/low-level width
t
KH2
, t
KL2
<100>
REGC = Capacity, V
DD
= 4.0 to 5.5 V,
REGC = V
DD
= 2.7 to 5.5 V
90
ns
REGC = V
DD
= 4.0 to 5.5 V
30
ns
SI0n setup time (to SCK0n
↑
)
t
SIK2
<101>
REGC = Capacity, V
DD
= 4.0 to 5.5 V,
REGC = V
DD
= 2.7 to 5.5 V
60
ns
REGC = V
DD
= 4.0 to 5.5 V
30
ns
SI0n hold time (from SCK0n
↑
)
t
KSI2
<102>
REGC = Capacity, V
DD
= 4.0 to 5.5 V,
REGC = V
DD
= 2.7 to 5.5 V
60
ns
REGC = V
DD
= 4.0 to 5.5 V
50
ns
Delay time from SCK0n
↓
to SO0n
output
t
KSO2
<103>
REGC = Capacity, V
DD
= 4.0 to 5.5 V,
REGC = V
DD
= 2.7 to 5.5 V
100
ns
Remark
n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)