參數(shù)資料
型號(hào): UPD70320L-8
廠商: NEC Corp.
英文描述: V25TM 16/8-BIT SINGLE-CHIP MICROCONTROLLER
中文描述: V25TM 16/8-BIT單片機(jī)
文件頁(yè)數(shù): 29/74頁(yè)
文件大?。?/td> 439K
代理商: UPD70320L-8
2
μ
P
ROL
ROR
reg,1
mem,1
reg,CL
mem,CL
reg,imm8
mem,imm8
reg,1
mem,1
reg,CL
mem,CL
reg,imm8
mem,imm8
Operation Code
1 1 0 1 0 0 0 W
1 1 0 1 0 0 0 W
1 1 0 1 0 0 1 W
1 1 0 1 0 0 1 W
1 1 0 0 0 0 0 W
1 1 0 0 0 0 0 W
1 1 0 1 0 0 0 W
1 1 0 1 0 0 0 W
1 1 0 1 0 0 1 W
1 1 0 1 0 0 1 W
1 1 0 0 0 0 0 W
1 1 0 0 0 0 0 W
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
2
2 to 4
2
2 to 4
3
3 to 5
2
2 to 4
2
2 to 4
3
3 to 5
Bytes
Flags
AC CY V
P
S
Z
CY
reg MSB, reg
reg
×
2 + CY
reg MSB
CY: V
1
reg MSB = CY: V
0
CY
(mem) MSB, (mem)
(mem)
×
2 + CY
(mem) MSB
CY: V
1
(mem) MSB = CY: V
0
The following operations are repeated while temp
CL
and temp
0.
CY
reg MSB, reg
reg
×
2 + CY
temp
temp – 1
The following operations are repeated while temp
CL
and temp
0.
CY
(mem) MSB, (mem)
(mem)
×
2 + CY
temp
temp – 1
The following operations are repeated while temp
imm8
and temp
0.
CY
reg MSB, reg
reg
×
2 + CY
temp
temp – 1
The following operations are repeated while temp
imm8
and temp
0.
CY
(mem) MSB, (mem)
(mem)
×
2 + CY
temp
temp – 1
CY
reg LSB, reg
reg
÷
2
reg MSB
CY
reg MSB
bit following reg MSB: V
1
reg MSB = bit following reg MSB: V
0
CY
(mem) LSB, (mem)
(mem)
÷
2
(mem) MSB
CY
(mem) MSB
bit following (mem) MSB: V
1
(mem) MSB = bit following (mem) MSB: V
0
The following operations are repeated while temp
CL and temp
0.
CY
reg LSB, reg
reg
÷
2
reg MSB
CY
temp
temp – 1
The following operations are repeated while temp
CL and temp
0.
CY
(mem) LSB, (mem)
(mem)
÷
2
(mem) MSB
CY
temp
temp – 1
The following operations are repeated while temp
imm8 and temp
0.
CY
reg LSB, reg
reg
÷
2
reg MSB
CY
temp
temp – 1
The following operations are repeated while temp
imm8 and temp
0.
CY
(mem) LSB, (mem)
(mem)
÷
2
(mem) MSB
CY
temp
temp – 1
Operation
Rotate
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 0 0 1 reg
mod 0 0 1 mem
1 1 0 0 1 reg
mod 0 0 1 mem
1 1 0 0 1 reg
mod 0 0 1 mem
×
×
×
×
×
×
×
×
×
×
×
×
×
×
U
U
U
U
×
×
U
U
U
U
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