- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376430 > UPD703100AGJ-40-8EU (NEC Corp.) Circular Connector; No. of Contacts:56; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:25-4 RoHS Compliant: No PDF資料下載
參數(shù)資料
| 型號(hào)： | UPD703100AGJ-40-8EU |
| 廠商： | NEC Corp. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:56; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:25-4 RoHS Compliant: No |
| 中文描述： | V850E/MS1TM 32/16單晶片微控制器 |
| 文件頁(yè)數(shù)： | 102/132頁(yè) |
| 文件大?。?/td> | 1174K |
| 代理商： | UPD703100AGJ-40-8EU |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)當(dāng)前第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)
Preliminary Data Sheet U14168EJ2V0DS00
102
μ
PD703100A-33, 703100A-40, 703101A-33, 703102A-33
(e) Read timing (EDO DRAM) (1/3)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Data input setup time (to CLKOUT
↑
)
<26>
t
SKID
10
ns
Data input hold time (from CLKOUT
↑
)
<27>
t
HKID
2
ns
Data output delay time from OE
↑
<37>
t
DRDOD
(0.5 + i) T – 10
ns
Row address setup time
<56>
t
ASR
(0.5 + w
RP
) T – 10
ns
Row address hold time
<57>
t
RAH
(0.5 + w
RH
) T – 10
ns
Column address setup time
<58>
t
ASC
0.5T – 10
ns
Column address hold time
<59>
t
CAH
(0.5 + w
DA
) T – 10
ns
RAS precharge time
<61>
t
RP
(0.5 + w
RP
) T – 5
ns
Column address read time (from RAS
↑
)
<64>
t
RAL
(2 + w
CP
+ w
DA
) T – 10
ns
CAS-RAS precharge time
<66>
t
CRP
(1 + w
RP
) T – 10
ns
CAS hold time
<67>
t
CSH
(1.5 + w
RH
+ w
DA
)
T –
10
ns
WE setup time (to CAS
↓
)
<68>
t
RCS
(2 + w
RP
+ w
RH
) T – 10
ns
WE hold time (from RAS
↑
)
<69>
t
RRH
0.5T – 10
ns
WE hold time (from CAS
↑
)
<70>
t
RCH
1.5T – 10
ns
RAS access time
<73>
t
RAC
(2 + w
RH
+ w
DA
)
T –
20
ns
Access time from column address
<74>
t
AA
(1.5 + w
DA
) T – 20
ns
CAS access time
<75>
t
CAC
(1 + w
DA
) T – 20
ns
Column address delay time from RAS
<76>
t
RAD
(0.5 + w
RH
) T – 10
ns
RAS-CAS delay time
<77>
t
RCD
(1 + w
RH
) T – 10
ns
Output buffer turn-off delay time (from
OE)
<78>
t
OEZ
0
ns
Access time from CAS precharge
<80>
t
ACP
(1.5 + w
CP
+ w
DA
)
T –
20
ns
CAS precharge time
<81>
t
CP
(0.5 + w
CP
) T – 5
ns
RAS hold time for CAS precharge
<83>
t
RHCP
(2 + w
CP
+ w
DA
) T – 10
ns
Read cycle time
<93>
t
HPC
(1 + w
DA
+ w
CP
) T – 10
ns
RAS pulse width
<94>
t
RASP
(2.5 + w
RH
+ w
DA
)
T –
10
ns
CAS pulse width
<95>
t
HCAS
(0.5 + w
DA
) T – 10
ns
Off-page
<96>
t
OCH1
(2 + w
RH
+ w
DA
) T – 10
ns
CAS hold time from OE
On-page
<97>
t
OCH2
(0.5 + w
DA
) T – 10
ns
Data input hold time (from CAS
↓
)
<98>
t
DHC
0
ns
Remarks 1.
T = t
CYK
2.
w
RP
: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3.
w
RH
: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4.
w
DA
: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5.
w
CP
: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6.
i: the number of idle states that are inserted when a write cycle follows a read cycle.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD703100GJ-33-8EU | V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS |
| UPD703100GJ-40-8EU | V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS |
| UPD703100-33 | V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS |
| UPD703100-40 | V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS |
| UPD703100AF1-33-FA1 | V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD703100GJ-33-8EU | 制造商:NEC 制造商全稱:NEC 功能描述:V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS |
| UPD703100GJ-33-UEN | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD703100GJ-33-UEN-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD703100GJ-40-8EU | 制造商:NEC 制造商全稱:NEC 功能描述:V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS |
| UPD703100GJ-40-UEN | 制造商:Renesas Electronics Corporation 功能描述:MCU 32-bit V850E1 RISC ROMLess 3.3V/5V 144-Pin PQFP |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。