參數(shù)資料
型號(hào): UPD703100A-33
廠商: NEC Corp.
英文描述: V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: V850E/MS1TM 32/16單晶片微控制器
文件頁數(shù): 100/132頁
文件大?。?/td> 1174K
代理商: UPD703100A-33
Preliminary Data Sheet U14168EJ2V0DS00
100
μ
PD703100A-33, 703100A-40, 703101A-33, 703102A-33
(d) Write timing (high-speed page DRAM access: on-page) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Column address setup time
<58>
t
ASC
(0.5 + w
CP
) T – 10
ns
Column address hold time
<59>
t
CAH
(1.5 + w
DA
) T – 10
ns
RAS hold time
<63>
t
RSH
(1.5 + w
DA
) T – 10
ns
Column address read time (from RAS
)
<64>
t
RAL
(2 + w
CP
+ w
DA
) T – 10
ns
CAS pulse width
<65>
t
CAS
(1 + w
DA
) T – 10
ns
CAS precharge time
<81>
t
CP
(1 + w
CP
) T – 5
ns
RAS hold time for CAS precharge
<83>
t
RHCP
(2.5 + w
CP
+ w
DA
)
T – 10
ns
WE setup time (to CAS
)
<84>
t
WCS
w
CP
1
w
CP
T – 10
ns
WE hold time (from CAS
)
<85>
t
WCH
(1 + w
DA
) T – 10
ns
Data setup time (to CAS
)
<86>
t
DS
(0.5 + w
CP
) T – 10
ns
Data hold time (from CAS
)
<87>
t
DH
(1.5 + w
DA
) T – 10
ns
WE read time (from RAS
)
<88>
t
RWL
w
CP
= 0
(1.5 + w
DA
) T – 10
ns
WE read time (from CAS
)
<89>
t
CWL
w
CP
= 0
(1 + w
DA
) T – 10
ns
Data setup time (to WE
)
<90>
t
DSWE
w
CP
= 0
0.5T – 10
ns
Data hold time (from WE
)
<91>
t
DHWE
w
CP
= 0
(1.5 + w
DA
) T – 10
ns
WE pulse width
<92>
t
WP
w
CP
= 0
(1 + w
DA
) T – 10
ns
Remarks 1.
T = t
CYK
2.
w
CP
: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3.
w
DA
: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
相關(guān)PDF資料
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