參數(shù)資料
型號(hào)： UPD703034AY
廠商： NEC Corp.
英文描述： V850/SB2TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： V850/SB2TM 32-/16-BIT單晶片微控制器
文件頁(yè)數(shù)： 34/56頁(yè)
文件大小： 356K
代理商： UPD703034AY
Data Sheet U14780EJ1V0DS00
34
μ
PD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY
(c) Clock synchronous (T
A
= –40 to +85°C, V
DD
= BV
DD
= 4.0 to 5.5 V, V
SS
= BV
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Delay time from CLKOUT
↑
to address
<38>
t
DKA
0
19
ns
Delay time from CLKOUT
↑
to address
float
<39>
t
FKA
–12
10
ns
Delay time from CLKOUT
↓
to ASTB
<40>
t
DKST
0
19
ns
Delay time from CLKOUT
↑
to DSTB
<41>
t
DKD
0
19
ns
Data input setup time (to CLKOUT
↑
)
<42>
t
SIDK
20
ns
Data input hold time (from CLKOUT
↑
)
<43>
t
HKID
5
ns
Data output delay time from CLKOUT
↑
<44>
t
DKOD
19
ns
WAIT setup time (to CLKOUT
↓
)
<45>
t
SWTK
20
ns
WAIT hold time (from CLKOUT
↓
)
<46>
t
HKWT
5
ns
HLDRQ setup time (to CLKOUT
↓
)
<47>
t
SHQK
20
ns
HLDRQ hold time (from CLKOUT
↓
)
<48>
t
HKHQ
5
ns
Delay time from CLKOUT
↑
to address
float (during bus hold)
<49>
t
DKF
19
ns
Delay time from CLKOUT
↑
to HLDAK
<50>
t
DKHA
19
ns
Remark
The
values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1.
(d) Clock synchronous (T
A
= –40 to +85°C, V
DD
= 4.0 to 5.5 V, BV
DD
= 3.0 to 4.0 V, V
SS
= BV
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Delay time from CLKOUT
↑
to address
<38>
t
DKA
0
22
ns
Delay time from CLKOUT
↑
to address
float
<39>
t
FKA
–16
10
ns
Delay time from CLKOUT
↓
to ASTB
<40>
t
DKST
0
19
ns
Delay time from CLKOUT
↑
to DSTB
<41>
t
DKD
0
22
ns
Data input setup time (to CLKOUT
↑
)
<42>
t
SIDK
20
ns
Data input hold time (from CLKOUT
↑
)
<43>
t
HKID
5
ns
Data output delay time from CLKOUT
↑
<44>
t
DKOD
22
ns
WAIT setup time (to CLKOUT
↓
)
<45>
t
SWTK
24
ns
WAIT hold time (from CLKOUT
↓
)
<46>
t
HKWT
5
ns
HLDRQ setup time (to CLKOUT
↓
)
<47>
t
SHQK
24
ns
HLDRQ hold time (from CLKOUT
↓
)
<48>
t
HKHQ
5
ns
Delay time from CLKOUT
↑
to address
float (during bus hold)
<49>
t
DKF
19
ns
Delay time from CLKOUT
↑
to HLDAK
<50>
t
DKHA
19
ns
Remark
The
values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1.
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UPD703034B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:V850/SB1(TM).V850/SB2(TM) for Hardware | UM Including Electrical Characteristics[02/2003]
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