參數資料
型號： UPD703004A
廠商： NEC Corp.
英文描述： V853TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： V853TM 32-/16-BIT單晶片微控制器
文件頁數： 24/40頁
文件大?。?/td> 230K
代理商： UPD703004A
μ
PD703003A, 703004A, 703025A
24
Data Sheet U13188EJ4V0DS00
(5) Read timing (1/2)
Parameter
Symbol
Conditions
25 MHz Version
33 MHz Version
Unit
MIN.
MAX.
MIN.
MAX.
Delay time from CLKOUT
↑
to address
<20> t
DKA
3
20
3
20
ns
Delay time from CLKOUT
↑
to R/W, UBEN, LBEN
<78> t
DKA2
Delay time from CLKOUT
↑
to address float
<21> t
FKA
–2
3
+13
15
–2
3
+13
15
ns
ns
Delay time from CLKOUT
↓
to ASTB
<22> t
DKST
3
15
3
15
ns
Delay time from CLKOUT
↑
to DSTB
<23> t
DKD
3
15
3
15
ns
Data input setup time (to CLKOUT
↑
)
<24> t
SIDK
5
5
ns
Data input hold time (from CLKOUT
↑
)
<25> t
HKID
5
5
ns
WAIT setup time (to CLKOUT
↓
) <26> t
SWTK
5
5
ns
WAIT hold time (from CLKOUT
↓
)
<27> t
HKWT
5
5
ns
Address hold time (from CLKOUT
↑
)
<28> t
HKA
0
0
ns
Address setup time (to ASTB
↓
)
<29> t
SAST
–40
°
C
≤
T
A
≤
+70
°
C
0.5T – 10
0.5T – 10
ns
70
°
C < T
A
≤
85
°
C
0.5T – 12
0.5T – 12
ns
Address hold time (from ASTB
↓
) <30> t
HSTA
0.5T – 10
0.5T – 10
ns
Delay time from DSTB
↓
to address float
<31> t
FDA
0
0
ns
Data input setup time (to address)
<32> t
SAID
–40
°
C
≤
T
A
≤
+70
°
C
(2 + n)T – 22
(2 + n)T – 22
ns
70
°
C < T
A
≤
85
°
C
(2 + n)T – 25
(2 + n)T – 25
ns
Data input setup time (to DSTB
↓
)
<33> t
SDID
–40
°
C
≤
T
A
≤
+70
°
C
(1 + n)T – 20
(1 + n)T – 20
ns
70
°
C < T
A
≤
85
°
C
(1 + n)T – 24
(1 + n)T – 24
ns
Delay time from ASTB
↓
to DSTB
↓
<34> t
DSTD
0.5T – 10
0.5T – 10
ns
Data input hold time (from DSTB
↑
)
<35> t
HDID
0
0
ns
Delay time from DSTB
↑
to address output
<36> t
DDA
(1 + i)T
(1 + i)T
ns
Delay time from DSTB
↑
to ASTB
↑
<37> t
DDSTH
0.5T – 10
0.5T – 10
ns
Delay time from DSTB
↑
to ASTB
↓
<38> t
DDSTL
(1.5 + i)T – 10
(1.5 + i)T – 10
ns
DSTB low-level width
<39> t
WDL
–40
°
C
≤
T
A
≤
+70
°
C
(1 + n)T – 10
(1 + n)T – 10
ns
70
°
C < T
A
≤
85
°
C
(1 + n)T – 13
(1 + n)T – 13
ns
ASTB high-level width
<40> t
WSTH
T – 10
T – 10
ns
WAIT setup time (to address)
<41> t
SAWT1
n
≥
1, –40
°
C
≤
T
A
≤
+70
°
C
1.5T – 20
1.5T – 20
ns
n
≥
1, 70
°
C < T
A
≤
85
°
C
1.5T – 24
1.5T – 24
ns
<42> t
SAWT2
n
≥
1, –40
°
C
≤
T
A
≤
+70
°
C
(1.5 + n)T – 20
(1.5 + n)T – 20
ns
n
≥
1, 70
°
C < T
A
≤
85
°
C
(1.5 + n)T – 24
(1.5 + n)T – 24
ns
WAIT hold time (from address)
<43> t
HAWT1
n
≥
1
(0.5 + n)T
(0.5 + n)T
ns
<44> t
HAWT2
n
≥
1
(1.5 + n)T
(1.5 + n)T
ns
WAIT setup time (to ASTB
↓
)
<45> t
SSTWT1
n
≥
1, –40
°
C
≤
T
A
≤
+70
°
C
T – 18
T – 18
ns
n
≥
1, 70
°
C < T
A
≤
85
°
C
T – 20
T – 20
ns
<46> t
SSTWT2
n
≥
1
(1 + n)T – 15
(1 + n)T – 15
ns
WAIT hold time (from ASTB
↓
)
<47> t
HSTWT1
n
≥
1
nT
nT
ns
<48> t
HSTWT2
n
≥
1
(1 + n)T
(1 + n)T
ns
Remarks 1.
T = t
CYK
2.
n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may
vary when using the programmable wait insertion function.
3.
i indicates the number of idle states (0 or 1) that are inserted after a read cycle.
4.
Maintain at least one of the two data input hold times, either t
HKID
(<25>) or t
HDID
(<35>).
相關PDF資料
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