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參數(shù)資料

型號：	UPD703003GC
廠商：	NEC Corp.
英文描述：	V853TM 32/16-BIT SINGLE-CHIP MICROCONTROLLER
中文描述：	V853TM 32/16位單片機(jī)
文件頁數(shù)：	50/82頁
文件大?。?/td>	452K
代理商：	UPD703003GC

μ

PD703003

50

Data Sheet U12261EJ2V1DS00

Instruction

Mnemonic

group

Operand

Opcode

Operation

Flags

CY OV

S

Z

SAT

Arithmetic MULH

operation

instructions

reg1, reg2

r r r r r 0 0 01 1 1RRRRR

GR[reg2]

←

GR[reg2]

Note

×

GR[reg1]

Note

(signed multiplication)

MULH

imm5, reg2

r r r r r 0 1 01 1 1 i i i i i

GR[reg2]

←

GR[reg2]

Note

×

sign-extend (imm5)

(signed multiplication)

MULHI

imm16, reg1, reg2

r r r r r 1 1 01 1 1RRRRR

GR[reg2]

←

GR[reg1]

Note

×

imm16

i i i i i i i i i i i i i i i i

(signed multiplication)

DIVH

reg1, reg2

r r r r r 0 0 00 1 0RRRRR

GR[reg2]

←

GR[reg2]

÷

GR[reg1]

Note

(signed division)

×

×

×

CMP

reg1, reg2

r r r r r 0 0 11 1 1RRRRR

result

←

GR[reg2] – GR[reg1]

×

×

×

×

CMP

imm5, reg2

r r r r r 0 1 00 1 1 i i i i i

result

←

GR[reg2] – sign-extend (imm5)

×

×

×

×

SETF

cccc, reg2

r r r r r 1 1 11 1 10 c c c c

0 00 0 00 0 00 0 00 0 00 0

if conditions are satisfied

then GR[reg2]

←

00000001H

else GR[reg2]

←

00000000H

Saturated SATADD reg1, reg2

operation

SATADD imm5, reg2

instructions

SATSUB reg1, reg2

r r r r r 0 0 01 1 0RRRRR

GR[reg2]

←

saturated (GR[reg2] + GR[reg1])

×

×

×

×

×

r r r r r 0 1 00 0 1 i i i i i

GR[reg2]

←

saturated (GR[reg2] + sign-extend (imm5))

×

×

×

×

×

r r r r r 0 0 01 0 1RRRRR

GR[reg2]

←

saturated (GR[reg2] – GR[reg1])

×

×

×

×

×

SATSUBI imm16, reg1, reg2

r r r r r 1 1 00 1 1RRRRR

i i i i i i i i i i i i i i i i

GR[reg2]

←

saturated (GR[reg1] – sign-extend (imm16))

×

×

×

×

×

SATSUBR

reg1, reg2

r r r r r 0 0 01 0 0RRRRR

GR[reg2]

←

saturated (GR[reg1] – GR[reg2])

×

×

×

×

×

Logical

operation

instruction

TST

reg1, reg2

r r r r r 0 0 10 1 1RRRRR

result

←

GR[reg2]AND GR[reg1]

0

×

×

OR

reg1, reg2

r r r r r 0 0 10 0 0RRRRR

GR[reg2]

←

GR[reg2]OR GR[reg1]

0

×

×

ORI

imm16, reg1, reg2

r r r r r 1 1 01 0 0RRRRR

GR[reg2]

←

GR[reg1]OR zero-extend (imm16)

i i i i i i i i i i i i i i i i

0

×

×

AND

reg1, reg2

r r r r r 0 0 10 1 0RRRRR

GR[reg2]

←

GR[reg2]AND GR[reg1]

0

×

×

ANDI

imm16, reg1, reg2

r r r r r 1 1 01 1 0RRRRR

GR[reg2]

←

GR[reg1]AND zero-extend (imm16)

i i i i i i i i i i i i i i i i

0

0

×

XOR

reg1, reg2

r r r r r 0 0 10 0 1RRRRR

GR[reg2]

←

GR[reg2]XOR GR[reg1]

0

×

×

XORI

imm16, reg1, reg2

r r r r r 1 1 01 0 1RRRRR

GR[reg2]

←

GR[reg1]XOR zero-extend (imm16)

i i i i i i i i i i i i i i i i

0

×

×

NOT

reg1, reg2

r r r r r 0 0 00 1RRRRR

GR[reg2]

←

NOT (GR[reg1])

0

×

×

SHL

reg1, reg2

r r r r r 1 1 11 1 1RRRRR

0 00 0 00 0 01 1 00 0 00 0

GR[reg2]

←

GR[reg2]logically shift left by GR[reg1]

×

0

×

×

SHL

imm5, reg2

r r r r r 0 1 01 1 0 i i i i i

GR[reg2]

←

GR[reg2]logically shift left by

×

0

×

×

zero-extend (imm5)

SHR

reg1, reg2

r r r r r 1 1 11 1 1RRRRR

0 00 0 00 0 01 0 00 0 00 0

GR[reg2]

←

GR[reg2]logically shift right by GR[reg1]

×

0

×

×

SHR

imm5, reg2

r r r r r 0 1 01 0 0 i i i i i

GR[reg2]

←

GR[reg2]logically shift right by

×

0

×

×

zero-extend (imm5)

SAR

reg1, reg2

r r r r r 1 1 11 1 1RRRRR

GR[reg2]

←

GR[reg2]arithmetically shift right by

0 00 0 00 0 01 0 10 0 00 0

×

0

×

×

GR[reg1]

SAR

imm5, reg2

r r r r r 0 1 01 0 1 i i i i i

GR[reg2]

←

GR[reg2]arithmetically shift right by

×

0

×

×

zero-extend (imm5)

Note

Only the low-order half word is valid.

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
UPD703003GC-25	制造商:NEC 制造商全稱:NEC 功能描述:V853TM 32/16-BIT SINGLE-CHIP MICROCONTROLLER
UPD703003GC-25-XXX-7EA	制造商:未知廠家制造商全稱:未知廠家功能描述:32-Bit Microcontroller
UPD703003GC-33	制造商:NEC 制造商全稱:NEC 功能描述:V853TM 32/16-BIT SINGLE-CHIP MICROCONTROLLER
UPD703003GC-33-XXX-7EA	制造商:未知廠家制造商全稱:未知廠家功能描述:32-Bit Microcontroller
UPD703004A	制造商:NEC 制造商全稱:NEC 功能描述:V853TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS

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