參數(shù)資料
型號(hào)： UPD703003GC-33
廠商： NEC Corp.
英文描述： V853TM 32/16-BIT SINGLE-CHIP MICROCONTROLLER
中文描述： V853TM 32/16位單片機(jī)
文件頁數(shù)： 64/82頁
文件大小： 452K
代理商： UPD703003GC-33
μ
PD703003
64
Data Sheet U12261EJ2V1DS00
(5) Read timing (1/2)
Parameter
Symbol
Conditions
25-MHz Version
33-MHz Version
Units
MIN.
MAX.
MIN.
MAX.
CLKOUT
↑
→
address delay time <20> t
DKA
3
20
3
20
ns
CLKOUT
↑
→
R/W, UBEN, LBEN delay time
<78> t
DKA2
–2
+13
–2
+13
ns
CLKOUT
↑
→
address float delay time
<21> t
FKA
3
15
3
15
ns
CLKOUT
↓
→
ASTB delay time
<22> t
DKST
–2
+13
–2
+13
ns
CLKOUT
↑
→
DSTB delay time
<23> t
DKD
–2
+13
–2
+13
ns
Data input setup time (to CLKOUT
↑
)
<24> t
SIDK
7
7
ns
Data input hold time (from CLKOUT
↑
)
<25> t
HKID
5
5
ns
WAIT setup time (to CLKOUT
↓
) <26> t
SWTK
8
8
ns
WAIT hold time (from CLKOUT
↓
)
<27> t
HKWT
5
5
ns
Address hold time (from CLKOUT
↑
)
<28> t
HKA
0
0
ns
Address setup time (to ASTB
↓
)
<29> t
SAST
0.5T – 10
0.5T – 10
ns
Address hold time (from ASTB
↓
) <30> t
HSTA
0.5T – 10
0.5T – 10
ns
DSTB
↓
→
address float delay time
<31> t
FDA
0
0
ns
Data input setup time (to address)
<32> t
SAID
(2 + n)T – 20
(2 + n)T – 20
ns
Data input setup time (to DSTB
↓
)
<33> t
SDID
(1 + n)T – 20
(1 + n)T – 20
ns
ASTB
↓
→
DSTB
↓
delay time
<34> t
DSTD
0.5T – 10
0.5T – 10
ns
Data input hold time (from DSTB
↑
)
<35> t
HDID
0
0
ns
DSTB
↑
→
address output delay time
<36> t
DDA
(1 + i)T – 3
(1 + i)T – 3
ns
DSTB
↑
→
ASTB
↑
delay time
<37> t
DDSTH
0.5T – 10
0.5T – 10
ns
DSTB
↑
→
ASTB
↓
delay time
<38> t
DDSTL
(1.5 + i)T – 10
(1.5 + i)T – 10
ns
DSTB low-level width
<39> t
WDL
(1 + n)T – 10
(1 + n)T – 10
ns
ASTB high-level width
<40> t
WSTH
T – 10
T – 10
ns
WAIT setup time (to address)
<41> t
SAWT1
n
≥
1
1.5T – 20
1.5T – 20
ns
<42> t
SAWT2
(1.5 + n)T – 20
(1.5 + n)T – 20
ns
WAIT hold time (from address)
<43> t
HAWT1
n
≥
1
(0.5 + n)T
(0.5 + n)T
ns
<44> t
HAWT2
(1.5 + n)T
(1.5 + n)T
ns
WAIT setup time (to ASTB
↓
)
<45> t
SSTWT1
n
≥
1
T – 15
T – 15
ns
<46> t
SSTWT2
(1 + n)T – 15
(1 + n)T – 15
ns
WAIT hold time (from ASTB
↓
)
<47> t
HSTWT1
n
≥
1
nT
nT
ns
<48> t
HSTWT2
(1 + n)T
(1 + n)T
ns
Remarks 1.
T = t
CYK
2.
n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may
vary when using the programmable wait insertion function.
3.
i indicates the number of idle states (0 or 1) that are inserted after a read cycle.
4.
Maintain at least one of the two data input hold times, either t
HKID
(<25>) or t
HDID
(<35>).
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