參數(shù)資料
型號： UPD703003GC-25
廠商： NEC Corp.
英文描述： V853TM 32/16-BIT SINGLE-CHIP MICROCONTROLLER
中文描述： V853TM 32/16位單片機
文件頁數(shù)： 52/82頁
文件大?。?/td> 452K
代理商： UPD703003GC-25
μ
PD703003
52
Data Sheet U12261EJ2V1DS00
Instruction
Mnemonic
group
Operand
Opcode
Operation
Flags
CY OV
S
Z
SAT
Special
LDSR
reg2, regID
r r r r r 1 1 11 1 1RRRRR
SR[regID]
←
GR[reg2]
0 00 0 00 0 00 0 10 0 00 0
Note
regID = EIPC, FEPC
instructions
regID = EIPSW, FEPSW
regID = PSW
×
×
×
×
×
STSR
regID, reg2
r r r r r 1 1 11 1 1RRRRR
GR[reg2]
←
SR[regID]
0 00 0 00 0 00 1 00 0 00 0
TRAP
vector
0 00 0 01 1 11 1 1 i i i i i
0 00 0 00 0 10 0 00 0 00 0
EIPC
←
PC + 4 (restored PC)
EIPSW
←
PSW
ECR.EICC
←
Interrupt code
PSW.EP
←
1
PSW.ID
←
1
PC
←
00000040H (when vector is 00H to 0FH)
00000050H (when vector is 10H to 1FH)
RETI
0 00 0 01 1 11 1 10 0 00 0
0 00 0 00 0 10 1 00 0 00 0
if PSW.EP = 1
then PC
←
EIPC
PSW
←
EIPSW
else if PSW.NP = 1
then PC
←
FEPC
PSW
←
FEPSW
else PC
←
EIPC
PSW
←
EIPSW
R
R R R R
HALT
0 00 0 01 1 11 1 10 0 00 0
0 00 0 00 0 10 0 10 0 00 0
Stops
DI
0 00 0 01 1 11 1 10 0 00 0
0 00 0 00 0 10 1 10 0 00 0
PSW.ID
←
1
(maskable interrupt prohibit)
EI
1 00 0 01 1 11 1 10 0 00 0
0 00 0 00 0 10 1 10 0 00 0
PSW.ID
←
0
(maskable interrupt enable)
NOP
0 00 0 00 0 00 0 00 0 00 0
No operation, uses at least one clock
Note
In this instructions, “reg2” is the mnemonic abbreviation for the source register, but the reg1 field is used
for the opcode. Consequently, these instructions differ from other instructions in a way registers are
specified in mnemonics description and opcodes.
rrrrr = regID specification
RRRRR = reg2 specification
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相關代理商/技術參數(shù)
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