參數(shù)資料
型號： UPD70216H
廠商： NEC Corp.
英文描述： V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR
中文描述： V40HLTM，V50HLTM 16 / 8，16位微處理器
文件頁數(shù)： 46/110頁
文件大小： 625K
代理商： UPD70216H
4
μ
P
D
AC CY V
P
S
Z
Instruc-
tion
Group
Mnemonic
Operand(s)
Operation
Operation Code
Flags
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
reg8
mem8
reg16
mem16
reg8
mem8
reg16
mem16
reg16,
(reg16’,)
Note
imm8
reg16,
mem16,
imm8
reg16,
(reg16’,)
Note
imm16
reg16,
mem16,
imm16
1 1 1 1 0 1 1 0
1 1 1 1 0 1 1 0
1 1 1 1 0 1 1 1
1 1 1 1 0 1 1 1
1 1 1 1 0 1 1 0
1 1 1 1 0 1 1 0
1 1 1 1 0 1 1 1
1 1 1 1 0 1 1 1
0 1 1 0 1 0 1 1
0 1 1 0 1 0 1 1
0 1 1 0 1 0 0 1
0 1 1 0 1 0 0 1
1 1 1 0 0 reg
mod
1 0 0 mem
1 1 1 0 0 reg
mod
1 0 0 mem
1 1 1 0 1 reg
mod
1 0 1 mem
1 1 1 0 1 reg
mod
1 0 1 mem
1 1 reg reg’
mod reg mem
1 1 reg reg’
mod reg mem
2
2-4
2
2-4
2
2-4
2
2-4
3
3-5
4
4-6
U
×
×
U
U
U
U
×
×
U
U
U
U
×
×
U
U
U
U
×
×
U
U
U
U
×
×
U
U
U
U
×
×
U
U
U
U
×
×
U
U
U
U
×
×
U
U
U
U
×
×
U
U
U
U
×
×
U
U
U
U
×
×
U
U
U
U
×
×
U
U
U
AW
←
AL
×
reg8
AH = 0: CY
←
0, V
←
0
AH
≠
0: CY
←
1, V
←
1
AW
←
AL
×
(mem8)
AH = 0: CY
←
0, V
←
0
AH
≠
0: CY
←
1, V
←
1
DW, AW
←
AW
×
reg16
DW = 0: CY
←
0, V
←
0
DW
≠
0: CY
←
1, V
←
1
DW, AW
←
AW
×
(mem16)
DW = 0: CY
←
0, V
←
0
DW
≠
0: CY
←
1, V
←
1
AW
←
AL
×
reg8
AH = AL sign extension: CY
←
0, V
←
0
AH
≠
AL sign extension: CY
←
1, V
←
1
AW
←
AL
×
(mem8)
AH = AL sign extension: CY
←
0, V
←
0
AH
≠
AL sign extension: CY
←
1, V
←
1
DW, AW
←
AW
×
reg16
DW = AW sign extension: CY
←
0, V
←
0
DW
≠
AW sign extension: CY
←
1, V
←
1
DW, AW
←
AW
×
(mem16)
DW = AW sign extension: CY
←
0, V
←
0
DW
≠
AW sign extension: CY
←
1, V
←
1
reg16
←
reg16’
×
imm8
Product
≤
16 bits : CY
←
0, V
←
0
Product > 16 bits : CY
←
1, V
←
1
reg16
←
(mem16)
×
imm8
Product
≤
16 bits : CY
←
0, V
←
0
Product > 16 bits : CY
←
1, V
←
1
reg16
←
reg16’
×
imm16
Product
≤
16 bits : CY
←
0, V
←
0
Product > 16 bits : CY
←
1, V
←
1
reg16
←
(mem16)
×
imm16
Product
≤
16 bits : CY
←
0, V
←
0
Product > 16 bits : CY
←
1, V
←
1
21-22
26-27
29-30
38-39
33-39
38-44
41-47
50-56
28-34
37-43
36-42
45-51
MULU
MUL
M
Note
The 2nd operand can be omitted, in which case the same register as the 1st operand is taken as being specified.
Bytes
Clock Cycles
V40HL V50HL
21-22
26-27
29-30
34-35/
38-39
33-39
38-44
41-47
46-52/
50-56
28-34
33-39/
37-43
36-42
41-47/
45-51
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