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參數(shù)資料
| 型號： | UPD65977S1-XXX-B6 |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件頁數(shù)： | 25/64頁 |
| 文件大?。?/td> | 399K |
| 代理商： | UPD65977S1-XXX-B6 |
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25
μ
PD64A, 65
Data Sheet U14380EJ2V0DS00
5.3 Standby Mode Release Timing
(1) STOP Mode Release Timing
Figure 5-1. STOP Mode Release by Release Condition
Caution When a release condition is established in the STOP mode, the device is released from the STOP
mode, and goes into a wait state. At this time, if the release condition is not held, the device
goes into STOP mode again after the wait time has elapsed. Therefore, when releasing the STOP
mode, it is necessary to hold the release condition longer than the wait time.
(2) HALT Mode Release Timing
Figure 5-2. HALT Mode Release by Release Condition
HALT mode
OPERATING mode
Oscillation
OPERATING
mode
HALT instruction
(HALT mode)
Standby
release signal
Clock
Wait
(52/f
X
+
α
)
HALT mode
OPERATING
mode
STOP mode
Oscillation
stopped
Oscillation
OPERATING
mode
Oscillation
HALT instruction
(STOP mode)
Standby
release signal
Clock
α
: Oscillation growth time
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