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參數(shù)資料
| 型號： | UPD65703 |
| 英文描述： | ISSP Series Pamphlet | Pamphlet[11/2002] |
| 中文描述： | 心理學(xué)會系列小冊子|小冊子[11/2002] |
| 文件頁數(shù)： | 12/64頁 |
| 文件大?。?/td> | 399K |
| 代理商： | UPD65703 |
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12
μ
PD64A, 65
Data Sheet U14380EJ2V0DS00
2.8 Arithmetic and Logic Unit (ALU): 4 Bits
The arithmetic and logic unit (ALU), which refers to an arithmetic circuit consisting of 4 bits, executes simple
manipulations with priority given to logical operations.
2.9 Flags
2.9.1 Status flag (F)
Pin and timer statuses can be checked by executing the STTS instruction to check the status flag.
The status flag is set (to 1) in the following cases.
If the condition specified with the operand is met when the STTS instruction has been executed
When STANDBY mode is released.
When the release condition is met at the point of executing the HALT instruction. (In this case, the system
is not placed in STANDBY mode.)
Conversely, the status flag is cleared (to 0) in the following cases:
If the condition specified with the operand is not met when the STTS instruction has been executed.
When the status flag has been set (to 1), the HALT instruction executed, but the release condition is not met
at the point of executing the HALT instruction. (In this case, the system is not placed in STANDBY mode.)
Table 2-1. Conditions for Status Flag (F) To Be Set by STTS Instruction
Operand Value of STTS Instruction
Condition for Status Flag (F) To Be Set
b
3
b
2
b
1
b
0
0
0
0
0
High level is input to at least one of K
I
pins.
0
1
1
High level is input to at least one of K
I
pins.
1
1
0
High level is input to at least one of K
I
pins.
1
0
1
The down counter of the timer is 0.
1
Either of the combinations
of b
2
, b
1
, and b
0
above.
[The following condition is added in addition to the above.]
High level is input to at least one of S
0
, S
1
, and S
2
Note
pins.
Note
The use of STOP mode release for the S
2
pin must be enabled (bit 3 of P4 register is set to 1.)
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