參數(shù)資料
型號: UPD65650-QFP160P1.2SQ
英文描述: ASIC
中文描述: 專用集成電路
文件頁數(shù): 50/64頁
文件大?。?/td> 399K
代理商: UPD65650-QFP160P1.2SQ
50
μ
PD64A, 65
Data Sheet U14380EJ2V0DS00
AC Characteristics (T
A
= –40 to +85
°
C, V
DD
= 2.0 to 3.6 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Command execution time
t
CY
7.9
27
μ
s
μ
s
μ
s
μ
s
K
I
, S
0
, S
1
, S
2
high-level
t
H
10
width
When releasing STANDBY mode
In HALT mode
10
In STOP mode
Note
Note
10 + 52/f
X
+ oscillation growth time
Remark
t
CY
= 64/f
X
(f
X
: System clock oscillator frequency)
POC Circuit (T
A
= –40 to +85
°
C)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
POC-detected voltage
Note
V
POC
1.85
2.0
V
Note
Refers to the voltage with which the POC circuit cancels an internal reset. If VP
OC
< V
DD
, the internal reset
is released.
From the time of V
POC
V
DD
until the internal reset takes effect, lag of up to 1 ms occurs. When the period
of V
POC
V
DD
lasts less than 1 ms, the internal reset may not take effect.
System Clock Oscillation Circuit Characteristics (T
A
= –40 to +85
°
C, V
DD
= 2.0 to 3.6 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Oscillator frequency
f
X
2.4
3.64
8.0
MHz
(ceramic resonator)
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