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參數(shù)資料
| 型號： | UPD65569 |
| 英文描述： | CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003] |
| 中文描述： | CMOS門陣列Array.Embedded的包版本2.0 |設(shè)計手冊[05/2003] |
| 文件頁數(shù)： | 23/64頁 |
| 文件大小： | 399K |
| 代理商： | UPD65569 |
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23
μ
PD64A, 65
Data Sheet U14380EJ2V0DS00
5.2 Standby Mode Setup and Release
The standby mode is set with the HALT #b
3
b
2
b
1
b
0
B instruction for both STOP mode and HALT mode. For the
standby mode to be set, the status flag (F) is required to have been cleared (to 0).
The standby mode is released by the release condition specified with the reset (POC) or the operand of HALT
instruction. If the standby mode is released, the status flag (F) is set (to 1).
Even when the HALT instruction is executed in the state that the status flag (F) has been set (to 1), the standby
mode is not set. If the release condition is not met at this time, the status flag is cleared (to 0). If the release condition
is met, the status flag remains set (to 1).
Even in the case when the release condition has been already met at the point that the HALT instruction is
executed, the standby mode is not set. Here, also, the status flag (F) is set (to 1).
Caution Depending on the status of the status flag (F), the HALT instruction may not be executed. Be
careful about this. For example, when setting HALT mode after checking the key status with
the STTS instruction, the system does not enter HALT mode as long as the status flag (F)
remains set (to 1) thus sometimes performing an unintended operation. In this case, the
intended operation can be realized by executing the STTS instruction immediately after timer
setting to clear (to 0) the status flag.
Example
STTS
#03H
;To check the K
I
pin status.
MOV
STTS
T, #0xxH
#05H
(During this time, be sure not to execute an instruction that may set the status flag.)
#05H
;To set HALT mode
;To set the timer
;To clear the status flag
HALT
Table 5-2. Addresses Executed after Standby Mode Release
Release Condition
Address Executed after Release
Reset
0 address
Release condition shown in Table 5-3
The address following the HALT instruction
…
…
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| UPD65571 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003] |
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