參數(shù)資料
型號： UPD65367
英文描述： CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003]
中文描述： CMOS門陣列Array.Embedded的包版本2.0 |設(shè)計手冊[05/2003]
文件頁數(shù)： 22/64頁
文件大?。?/td> 399K
代理商： UPD65367
22
μ
PD64A, 65
Data Sheet U14380EJ2V0DS00
5. STANDBY FUNCTION
5.1 Outline of Standby Function
To save current consumption, two types of standby modes, i.e., HALT mode and STOP mode, are made available.
In STOP mode, the system clock stops oscillation. At this time, the X
IN
and X
OUT
pins are fixed at a low level.
In HALT mode, CPU operation halts, while the system clock continues oscillation. When in HALT mode, the
timer (including REM output and LED output) operates.
In either STOP mode or HALT mode, the statuses of the data memory, accumulator, and port register, etc.
immediately before the standby mode is set are retained. Therefore, make sure to set the port status for the system
so that the current consumption of the whole system is suppressed before the standby mode is set.
Table 5-1. Statuses during Standby Mode
STOP Mode
HALT Mode
Setting instruction
HALT instruction
Clock oscillation circuit
Oscillation stopped
Oscillation continued
CPU
Operation halted
Data memory
Immediately preceding status retained
Operation
Accumulator
Immediately preceding status retained
statuses
Flag
F
0 (When 1, the flag is not placed in the standby mode.)
CY
Immediately preceding status retained
Port register
Timer
Immediately preceding status retained
Operation halted
(The count value is reset to “0”)
Operable
Cautions
1. Write the NOP instruction as the first instruction after STOP mode is released.
2. When standby mode is released, the status flag (F) is set (to 1).
3. If, at the point the standby mode has been set, its release condition is met, then the system
is not placed in the standby mode. However, the status flag (F) is set (1).
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UPD65370 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003]
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